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公开(公告)号:US10467140B2
公开(公告)日:2019-11-05
申请号:US15099119
申请日:2016-04-14
Applicant: ARM Limited
Inventor: Roko Grubisic , Hakan Persson , Neil Andrew Jameson
IPC: G06F12/0831 , G06F9/46 , G06F12/128 , G06F12/1027
Abstract: An apparatus has a cache configured to store entries which correspond to blocks of addresses having one of a plurality of sizes as selected by a control device. When the control device has not yet indicated which size to use, cache access circuitry assumes a default size which is greater than at least one of the plurality of sizes.