公开(公告)号：US11086626B2

公开(公告)日：2021-08-10

申请号：US16662396

申请日：2019-10-24

Applicant: Arm Limited

Inventor： Roko Grubisic ,  Giacomo Gabrielli ,  Matthew James Horsnell ,  Syed Ali Mustafa Zaidi

IPC: G06F9/34 ,  G06F9/38 ,  G06F9/30 ,  G06F8/41

Abstract: Circuitry comprises decode circuitry to decode program instructions including producer instructions and consumer instructions, a consumer instruction requiring, as an input operand, a result generated by execution of a producer instruction; and execution circuitry to execute the program instructions; in which: the decode circuitry is configured to control operation of the execution circuitry in response to hint data associated with a given producer instruction and indicating, for the given producer instruction, a number of consumer instructions which require, as an input operand, a result generated by the given producer instruction.

公开(公告)号：US10055151B2

公开(公告)日：2018-08-21

申请号：US15256942

申请日：2016-09-06

Applicant: ARM LIMITED

Inventor： Roko Grubisic ,  Häkan Lars-Göran Persson ,  Georgia Kouveli

IPC: G06F12/08 ,  G06F3/06 ,  G06F12/1018 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/0804 ,  G06F12/0866

CPC classification number: G06F3/0619 ,  G06F3/0644 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0804 ,  G06F12/0864 ,  G06F12/0866 ,  G06F12/0895 ,  G06F12/1018 ,  Y02D10/13

Abstract: A data storage device comprises an array of data storage elements arranged as multiple partitions each comprising two or more data storage elements, each data storage element being associated with a respective identifier which identifies a data item currently stored by that data storage element; a predictor configured to compare, for each partition, information derived from the identifiers associated with the data storage elements of that partition with information derived from an identifier associated with the required data item, to identify a subset of partitions that do not store the required data item; and a comparator configured to compare identifiers associated with data storage elements of one or more partitions with the identifier associated with the required data item, wherein any partitions in the subset of partitions are excluded from the test group of partitions.

公开(公告)号：US11561898B1

公开(公告)日：2023-01-24

申请号：US17509348

申请日：2021-10-25

Applicant: Arm Limited

Inventor： Roko Grubisic

IPC: G06F12/08 ,  G06F3/06 ,  G06F12/0802

Abstract: Apparatuses for address expansion and methods of address expansion are disclosed. Memory region definitions are stored, each comprising attribute data relevant to a respective memory region. In response to reception of a first address a region identifier indicative of a memory region to which the first address belongs is provided. Cache storage stores data in association with an address tag and in response to a cache miss a data retrieval request is generated. Address expansion circuitry is responsive to the data retrieval request to initiate a lookup for attribute data relevant to the memory region to which the first address belongs. The address expansion circuitry expands the first address in dependence on a base address forming part of the attribute data to generate an expanded second address, wherein the expanded second address is part of greater address space than the first address.

公开(公告)号：US10250709B2

公开(公告)日：2019-04-02

申请号：US15099244

申请日：2016-04-14

Applicant: ARM Limited

Inventor： Jesus Javier de los Reyes Darias ,  Hakan Persson ,  Roko Grubisic ,  Vinod Pisharath Hari Pai

IPC: H04L12/18 ,  H04L12/54 ,  H04L29/06 ,  H04L29/08 ,  H04L12/861 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0891

Abstract: A data processing apparatus has multiple caches and a controller for controlling the caches. The controller and caches communicate over a first network and a second network. The first network is used for unicast communication from the controller to a specific one of the caches. The second network is used for communication of a multicast communication from the controller to two or more of the caches.

公开(公告)号：US11210102B2

公开(公告)日：2021-12-28

申请号：US16695735

申请日：2019-11-26

Applicant: Arm Limited

Inventor： Roko Grubisic

IPC: G06F9/38

Abstract: An apparatus comprises processing circuitry to execute instructions from one or more of a plurality of execution contexts each associated with a respective execution context identifier; a cache; and a speculative buffer. Control circuitry controls allocation of data to the cache and the speculative buffer. A speculative entry, for which allocation is caused by a speculative memory access associated with a given execution context, is allocated to the speculative buffer instead of to the cache while the speculatively executed memory access instruction remains speculative. The speculative entry specifies, as a tagged execution context identifier, the execution context identifier associated with the given execution context. Presence of the speculative entry in the speculative buffer is prevented from being observable to execution contexts other than the execution context identified by the tagged execution context identifier.

公开(公告)号：US10467140B2

公开(公告)日：2019-11-05

申请号：US15099119

申请日：2016-04-14

Applicant: ARM Limited

Inventor： Roko Grubisic ,  Hakan Persson ,  Neil Andrew Jameson

IPC: G06F12/0831 ,  G06F9/46 ,  G06F12/128 ,  G06F12/1027

Abstract: An apparatus has a cache configured to store entries which correspond to blocks of addresses having one of a plurality of sizes as selected by a control device. When the control device has not yet indicated which size to use, cache access circuitry assumes a default size which is greater than at least one of the plurality of sizes.

公开(公告)号：US09678889B2

公开(公告)日：2017-06-13

申请号：US14579483

申请日：2014-12-22

Applicant: ARM Limited

Inventor： Roko Grubisic ,  Andrew Burdass ,  Daren Croxford ,  Isidoros Sideris

IPC: G06F12/00 ,  G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/304 ,  Y02D10/13

Abstract: Address translation circuitry and a method of operating such a translation circuitry are provided. The address translation circuitry is configured to receive a first address used in a first addressing system and to translate it into a second address used in a second addressing system. Translation pipeline circuitry has plural pipeline stages configured to translate the first address into the second address over the course of the plural pipeline stages. Address comparison circuitry is configured to identify an address match condition when a received first address at least partially matches a previously received first address. Insertion circuitry is configured to determine a stage of progress of the previously received first address in the plural pipeline stages and to cause content of the stage of progress of the previously received first address to be unchanged at a next pipeline cycle when the address comparison circuitry identifies the address match condition.