公开(公告)号：US20250068427A1

公开(公告)日：2025-02-27

申请号：US18454158

申请日：2023-08-23

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Alexander Cole SHULYAK ,  Rami Mohammad AL SHEIKH

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus has pointer storage to store pointer values for a plurality of pointers and increment circuitry, responsive to a series of increment events, to differentially increment the pointer values of the pointers. Training circuitry comprises tracker circuitry to maintain a plurality of tracker entries and cache circuitry to maintain a plurality of cache entries. Each tracker entry identifies a control flow instruction, and each cache entry stores a resolved behaviour of an instance of a control flow instruction identified by a tracker entry. For a given control flow instruction identified in a given tracker entry, the training circuitry performs a training process to seek to determine, as an associated pointer for the given control flow instruction, a pointer from amongst the plurality of pointers whose pointer value increments in a manner that meets a correlation threshold with occurrence of instances of the given control flow instruction. Promotion circuitry, responsive to detection of the correlation threshold being met for the given control flow instruction, allocates a prediction entry within prediction circuitry to identify the given control flow instruction and the associated pointer, and a behaviour record is established within the prediction entry identifying the resolved behaviour for one or more instances of the given control flow instruction. The behaviour record is arranged such that each resolved behaviour is associated with the pointer value of the associated pointer at the time that resolved behaviour was observed. Responsive to a prediction trigger associated with a replay of a given instance of the given control flow instruction, the prediction circuitry determines, in dependence on a current pointer value of the associated pointer, a predicted behaviour of the given instance of the given control flow instruction from the behaviour record within the prediction entry.

公开(公告)号：US20250068565A1

公开(公告)日：2025-02-27

申请号：US18455025

申请日：2023-08-24

Applicant: ARM Limited

Inventor： Houdhaifa BOUZGUARROU ,  Rami Mohammad AL SHEIKH ,  Guillaume BOLBENES

IPC: G06F12/0862

Abstract: Prediction circuitry generates a prediction associated with a prediction input address, for controlling a speculative action by a processor. The prediction circuitry comprises combiner circuitry to determine a combined prediction by applying a prediction combination function to a given address and sets of prediction information generated by a plurality of predictors corresponding to the given address. A combiner cache structure comprises combiner cache entries. A given combiner cache entry associated with an address indication indicates items of combined prediction information determined by the combiner circuitry for an address corresponding to the address indication and different combinations of possible values for the respective sets of prediction information. Combiner cache lookup circuitry looks up the combiner cache structure based on the prediction input address to identify a selected combiner cache entry, and generates the prediction based on a selected item of combined prediction information selected from the selected combiner cache entry based on the respective sets of prediction information generated by the predictors corresponding to the prediction input address.

公开(公告)号：US20250068939A1

公开(公告)日：2025-02-27

申请号：US18455053

申请日：2023-08-24

Applicant: ARM Limited

Inventor： Houdhaifa BOUZGUARROU ,  Rami Mohammad AL SHEIKH ,  Michael Brian SCHINZLER

IPC: G06N5/022

Abstract: Combiner circuitry generates a combined prediction associated with a given address based on combining respective sets of prediction information generated by two or more predictors. Predictor control circuitry determines, based on a lookup of a prediction input address in a combiner hint data structure, whether a second predictor lookup suppression condition is satisfied for the prediction input address indicating that the combined prediction that would be determined by the combiner circuitry for the prediction input address is likely to be derivable from a prediction outcome predicted by the first predictor for the prediction input address. If this condition is satisfied, a lookup of the second predictor is suppressed and the prediction associated with the prediction input address is generated based on the prediction outcome predicted by the first predictor for the prediction input address.

公开(公告)号：US20250085971A1

公开(公告)日：2025-03-13

申请号：US18462742

申请日：2023-09-07

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Alexander Cole SHULYAK ,  Rami Mohammad AL SHEIKH

IPC: G06F9/32 ,  G06F9/30

Abstract: A data processing apparatus includes pointer storage configured to store pointer values for pointers. Increment circuitry, responsive to one or more increment events, increments each of the pointer values in dependence on a corresponding live pointer value update condition from corresponding live pointer value update conditions. The corresponding live pointer value update condition is different for each of the pointers. History storage circuitry stores resolved behaviours of instances of a control flow instruction, each of the resolved behaviours being associated with one of the pointers. At least one of the live pointer value update conditions is changeable at runtime. Consequently, storage can be reduced as compared to a situation where all pointer value update conditions are active.

公开(公告)号：US20250013470A1

公开(公告)日：2025-01-09

申请号：US18346407

申请日：2023-07-03

Applicant: Arm Limited

Inventor： Rami Mohammad AL SHEIKH

IPC: G06F9/38

Abstract: Branch prediction circuitry comprising branch target prediction circuitry to, for an identified block of sequential instructions, generate a branch target prediction identifying a predicted branch target for a selected branch instruction in the block of sequential instructions; output circuitry to output the branch target prediction; and determination circuitry to determine whether at least one condition is met. The branch target prediction circuitry is responsive to the determination circuitry determining that the at least one condition is met to generate the branch target prediction to identify both the predicted branch target for the selected branch instruction and one or more further predicted branch targets for one or more further branch instructions in the block of sequential instructions.