公开(公告)号：US20170344367A1

公开(公告)日：2017-11-30

申请号：US15166467

申请日：2016-05-27

Applicant: ARM Limited

Inventor： Jonathan Curtis BEARD ,  Wendy ELSASSER ,  Shibo WANG

IPC: G06F9/30 ,  G06F12/0875 ,  G06F9/32 ,  G06F12/084

Abstract: A data processing apparatus includes a multi-level memory system, one or more first processing unit coupled to the memory system at a first level and one or more second processing units each coupled to the memory system at a second level. A first reorder buffer maintains data order during execution of instructions by the first and second processing units and a second reorder buffer maintains data order during execution of the instructions by an associated second processing unit. An entry in the first reorder buffer is configured, dependent upon an indicator bit, as an entry for a single instruction or a pointer to an entry in the second reorder buffer. An entry in the second reorder buffer includes instruction block start and end addresses and indicators of input and output register. Instructions are released to a processing unit when all inputs, as indicated by the reorder buffers, are available.