公开(公告)号：US08918700B2

公开(公告)日：2014-12-23

申请号：US13764003

申请日：2013-02-11

Applicant: ARM Limited

Inventor： Michael Andrew Campbell ,  Thomas Kelshaw Conway

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1012 ,  G06F11/1048

Abstract: An apparatus includes encoding circuitry to generate code words for storage in a memory device. Decoding circuitry is responsive to a read transaction to decode one or more code words read from the memory device in order to generate read data for outputting in response to the read transaction. The decoding circuitry comprises error correction circuitry configured, for each read code word, to perform an error correction process to detect and correct errors in up to P symbols of the code word, where P is dependent on the number of ECC symbols in the code word. Error tracking circuitry determines error quantity indication data indicative of the errors detected by the error correction circuitry, and in response to the error quantity indication data indicating that an error threshold condition has been reached, the apparatus transitions from a normal mode of operation to a safety mode of operation.

Abstract translation: 一种装置包括编码电路以产生用于存储在存储器件中的代码字。 解码电路响应于读取事务来解码从存储器件读取的一个或多个代码字，以便产生用于响应于读取事务而输出的读取数据。 解码电路包括纠错电路，为每个读码字配置，执行纠错处理以检测和纠正代码字最多P个符号的错误，其中P取决于代码字中的ECC符号的数目 。 错误跟踪电路确定指示由纠错电路检测到的错误的错误量指示数据，并且响应于指示已经达到错误阈值条件的错误量指示数据，装置从正常操作模式转换到安全 操作模式。