公开(公告)号：US11232833B2

公开(公告)日：2022-01-25

申请号：US15679325

申请日：2017-08-17

Applicant: ARM Limited

Inventor： Abhishek B. Akkur ,  Jitendra Dasani ,  Shri Sagar Dwivedi ,  Vivek Nautiyal ,  Satinderjit Singh ,  Vasimraja Bhavikatti

IPC: G11C11/419 ,  H01L23/528 ,  H01L27/11 ,  G11C7/22 ,  G06F30/35 ,  G06F30/392 ,  G06F30/394 ,  G11C7/12 ,  G11C7/08 ,  G06F119/12

Abstract: A circuit includes a dummy wordline, a dummy bitline, and a dummy cell coupled to the dummy bitline. The dummy cell includes an active pulldown nMOSFET and a pass nMOSFET having a gate connected to the dummy wordline, a first source terminal connected to the drain terminal of the active pulldown nMOSFET, and a drain terminal connected to the dummy bitline. The circuit further includes a substrate-connected dummy bitline coupled to the source terminal of each active pulldown nMOSFET and coupled to a substrate.

公开(公告)号：US20190057735A1

公开(公告)日：2019-02-21

申请号：US15679325

申请日：2017-08-17

Applicant: ARM Limited

Inventor： Abhishek B. Akkur ,  Jitendra Dasani ,  Shri Sagar Dwivedi ,  Vivek Nautiyal ,  Satinderjit Singh ,  Vasimraja Bhavikatti

IPC: G11C11/419 ,  H01L23/528 ,  G06F17/50 ,  H01L27/11

Abstract: A circuit includes a dummy wordline, a dummy bitline, and a dummy cell coupled to the dummy bitline. The dummy cell includes an active pulldown nMOSFET and a pass nMOSFET having a gate connected to the dummy wordline, a first source terminal connected to the drain terminal of the active pulldown nMOSFET, and a drain terminal connected to the dummy bitline. The circuit further includes a substrate-connected dummy bitline coupled to the source terminal of each active pulldown nMOSFET and coupled to a substrate.

公开(公告)号：US09741445B1

公开(公告)日：2017-08-22

申请号：US15222532

申请日：2016-07-28

Applicant: ARM Limited

Inventor： Vasimraja Bhavikatti

IPC: G11C17/12 ,  H01L27/06

CPC classification number: G11C17/12 ,  H01L27/0688 ,  H01L27/11226

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a bitline. The integrated circuit may include a memory cell array having a plurality of memory cells. The integrated circuit may include a plurality of via paths coupling each of the memory cells to the bitline. The integrated circuit may include one or more open paths formed to decouple one or more memory cells from their corresponding via path to the bitline.