公开(公告)号：US20190325948A1

公开(公告)日：2019-10-24

申请号：US15960475

申请日：2018-04-23

申请人： Arm Limited

发明人： Vivek Nautiyal ,  Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC分类号： G11C11/419

摘要： Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.

公开(公告)号：US09824749B1

公开(公告)日：2017-11-21

申请号：US15256200

申请日：2016-09-02

申请人： ARM Limited

发明人： Vivek Nautiyal ,  Fakhruddin Ali Bohra ,  Satinderjit Singh ,  Shri Sagar Dwivedi ,  Abhishek B. Akkur

IPC分类号： G11C11/40 ,  G11C11/419 ,  G11C11/418 ,  G11C11/409 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C11/413

CPC分类号： G11C11/419 ,  G11C7/06 ,  G11C7/1048 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C11/409 ,  G11C11/413 ,  G11C2207/002 ,  G11C2207/12

摘要： Various implementations described herein are directed to an integrated circuit. The integrated circuit may include precharge circuitry for precharging bitlines to a source voltage level. The integrated circuit may include write assist circuitry having a charge storage element for providing a write assist signal to at least one of the bitlines. The integrated circuit may include read assist circuitry having a switching element for providing charge sharing between the bitlines, the precharge circuitry, and the charge storage element of the write assist circuitry.

公开(公告)号：US11232833B2

公开(公告)日：2022-01-25

申请号：US15679325

申请日：2017-08-17

申请人： ARM Limited

发明人： Abhishek B. Akkur ,  Jitendra Dasani ,  Shri Sagar Dwivedi ,  Vivek Nautiyal ,  Satinderjit Singh ,  Vasimraja Bhavikatti

IPC分类号： G11C11/419 ,  H01L23/528 ,  H01L27/11 ,  G11C7/22 ,  G06F30/35 ,  G06F30/392 ,  G06F30/394 ,  G11C7/12 ,  G11C7/08 ,  G06F119/12

摘要： A circuit includes a dummy wordline, a dummy bitline, and a dummy cell coupled to the dummy bitline. The dummy cell includes an active pulldown nMOSFET and a pass nMOSFET having a gate connected to the dummy wordline, a first source terminal connected to the drain terminal of the active pulldown nMOSFET, and a drain terminal connected to the dummy bitline. The circuit further includes a substrate-connected dummy bitline coupled to the source terminal of each active pulldown nMOSFET and coupled to a substrate.

公开(公告)号：US20210335397A1

公开(公告)日：2021-10-28

申请号：US16860764

申请日：2020-04-28

申请人： Arm Limited

发明人： Fakhruddin Ali Bohra ,  Lalit Gupta ,  Shri Sagar Dwivedi

IPC分类号： G11C7/10

摘要： Various implementations described herein are related to a device having memory circuitry having an array of memory cells. The device may include output circuitry coupled to the memory circuitry, and the output circuitry may have a first set of multiplexers that receives column data from the array of memory cells and provides first multiplexed output data. The device may include output interface circuitry coupled to the output circuitry, and the output interface circuitry may have a second set of multiplexers that receives the first multiplexed output data from the output circuitry and selectively provides second multiplexed output data based on a configurable mode of multiplexed operation.

公开(公告)号：US10755774B2

公开(公告)日：2020-08-25

申请号：US16820487

申请日：2020-03-16

申请人： Arm Limited

发明人： Vivek Nautiyal ,  Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC分类号： G11C11/00 ,  G11C11/419 ,  G11C11/412

摘要： Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.

公开(公告)号：US20200014373A1

公开(公告)日：2020-01-09

申请号：US16026946

申请日：2018-07-03

申请人： Arm Limited

发明人： Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Lalit Gupta ,  Yew Keong Chong ,  Gus Yeung

IPC分类号： H03K5/06 ,  G06F12/0804

摘要： Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.

公开(公告)号：US20200005836A1

公开(公告)日：2020-01-02

申请号：US16024449

申请日：2018-06-29

申请人： Arm Limited

发明人： Lalit Gupta ,  Fakhruddin Ali Bohra ,  Jitendra Dasani ,  Shri Sagar Dwivedi ,  Vivek Nautiyal ,  Gaurav Rattan Singla

IPC分类号： G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/14

摘要： Various implementations described herein refer to an integrated circuit having memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays. The first pair of bank arrays may have a first number of rows, and the second pair of bank arrays have a second number of rows that is different than the first number of rows. The integrated circuit may include bank multiplexer circuitry that is coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel. The bank multiplexer circuitry may provide an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal.

公开(公告)号：US20190325949A1

公开(公告)日：2019-10-24

申请号：US15960482

申请日：2018-04-23

申请人： Arm Limited

发明人： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra

IPC分类号： G11C11/419 ,  G11C11/412

摘要： Various implementations described herein may refer to an integrated circuit using discharging circuitries for bit lines. In one implementation, an integrated circuit may include a memory array having memory cells, where the memory cells are arranged into columns and configured to be accessed using bit line pairs. The integrated circuit may also include discharging circuitries to selectively discharge the bit line pairs, where a respective discharging circuitry is coupled to a negative supply voltage node of a respective column of memory cells. The respective discharging circuitry may discharge a bit line pair of the respective column to a first voltage when the bit line pair is selected for a memory operation, and may discharge the bit line pair of the respective column to a second voltage when the bit line pair is not selected for a memory operation, where the second voltage is greater than the first voltage.

公开(公告)号：US10217496B1

公开(公告)日：2019-02-26

申请号：US15907951

申请日：2018-02-28

申请人： Arm Limited

发明人： Vivek Nautiyal ,  Jitendra Dasani ,  Satinderjit Singh ,  Shri Sagar Dwivedi ,  Bo Zheng ,  Fakhruddin Ali Bohra

IPC分类号： G11C7/00 ,  G11C7/12 ,  G11C7/10 ,  G11C11/4097 ,  G11C11/419

摘要： Various implementations described herein are directed to an integrated circuit with memory circuitry having an array of bitcells that are accessible via multiple bitlines. The integrated circuit may include a write driver coupled to at least one bitline of the multiple bitlines through a column multiplexer. The integrated circuit may include a pass transistor coupled to the write driver and the column multiplexer via a write data line. The integrated circuit may include a charge storage device coupled between the pass transistor and write assist enable circuitry. The integrated circuit may include a transmission gate coupled to a gate of the write driver. The integrated circuit may include a clamp transistor coupled between the gate of write driver and the charge storage device such that the clamp transistor receives a voltage assist signal from the charge storage device at the gate of the write driver.

公开(公告)号：US11588477B2

公开(公告)日：2023-02-21

申请号：US17128800

申请日：2020-12-21

申请人： Arm Limited

发明人： Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Lalit Gupta ,  Yew Keong Chong ,  Gus Yeung

IPC分类号： H03K5/06 ,  G06F12/0804

摘要： Various implementations described herein are directed to an integrated circuit having clock generation circuitry that receives an input clock signal and provides a first clock signal having a first pulse width. The integrated circuit includes first pulse-stretching circuitry coupled between the clock generation circuitry and input latch control circuitry. The first pulse-stretching circuitry receives the first clock signal and provides a second clock signal to the input latch control circuitry based on an enable signal. The second clock signal has a second pulse width that is at least greater than the first pulse width. The integrated circuit may include second pulse-stretching circuitry coupled between the clock generation circuitry and read-write circuitry. The second pulse-stretching circuitry provides a third clock signal to the read-write circuitry based on the enable signal. The third clock signal has a third pulse width that is at least greater than the first pulse width.