公开(公告)号：US20230178538A1

公开(公告)日：2023-06-08

申请号：US18103313

申请日：2023-01-30

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Mudit Bhargava ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha

IPC: H01L27/02 ,  G06F30/31 ,  H01L21/768 ,  H01L23/535 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L27/0207 ,  G06F30/31 ,  H01L21/76898 ,  H01L23/535 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06544

Abstract: According to one implementation of the present disclosure, a method includes fabricating a memory macro unit; forming a through silicon via (TSV); and bonding the TSV at least partially through the fabricated memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.

公开(公告)号：US20190303523A1

公开(公告)日：2019-10-03

申请号：US15939047

申请日：2018-03-28

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Brian Tracy Cline ,  Stephen Lewis Moore ,  Saurabh Pijuskumar Sinha

IPC: G06F17/50 ,  H01L27/02 ,  H01L23/522

Abstract: Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without inter-tier-connection pairs. The method includes iteratively adjusting a location of the standard cells with or without a location of inter-tier connections so as to converge the location of the standard cells with or without the location of the inter-tier connections to optimized or legal locations.

公开(公告)号：US11120191B2

公开(公告)日：2021-09-14

申请号：US16820471

申请日：2020-03-16

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Brian Tracy Cline ,  Stephen Lewis Moore ,  Saurabh Pijuskumar Sinha

IPC: G06F30/392 ,  H01L27/02 ,  H01L23/522 ,  G06F111/04 ,  G06F111/20

Abstract: Various implementations described herein are directed to a method that defines tiers of an integrated circuit having standard cells placed adjacent to each other in a multi-tier placement. The integrated circuit includes multi-tier nets connected with inter-tier connections. The method includes pairing inter-tier connections as inter-tier-connection pairs belonging to a same net. The method includes grouping standard cells in groups with or without inter-tier-connection pairs from the tiers. The method includes relating the standard cells with or without inter-tier-connection pairs within each group from the groups by generating a multi-tier fence boundary around physical locations of the standard cells with or without inter-tier-connection pairs. The method includes iteratively adjusting a location of the standard cells with or without a location of inter-tier connections so as to converge the location of the standard cells with or without the location of the inter-tier connections to optimized locations or legal locations.

公开(公告)号：US10796053B2

公开(公告)日：2020-10-06

申请号：US16140461

申请日：2018-09-24

Applicant: Arm Limited

Inventor： Paul de Dood ,  Marlin Wayne Frederick, Jr. ,  Jerry Chaoyuan Wang ,  Brian Tracy Cline ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Sriram Thyagarajan ,  Gus Yeung ,  Daniel J. Albers ,  David William Granda

IPC: G06F17/50 ,  G06F30/39 ,  G06F30/30 ,  G06F30/398 ,  G06F30/392 ,  G06F30/394

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.

公开(公告)号：US11726116B2

公开(公告)日：2023-08-15

申请号：US17218686

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Zhiyao Xie ,  Shidhartha Das

IPC: G01R21/133 ,  G06F30/3308 ,  G05F1/66 ,  G06F30/367 ,  G01R31/317 ,  G05B13/02 ,  G05B15/02 ,  G06F119/06

CPC classification number: G01R21/133 ,  G01R31/31727 ,  G05B13/02 ,  G05B15/02 ,  G05F1/66 ,  G06F30/3308 ,  G06F30/367 ,  G06F2119/06

Abstract: An integrated circuit includes a first circuit and a power meter coupled to the first circuit at selected proxy locations. The power meter includes circuitry for generating toggle data, such as signal transitions or signal levels, from signals at the proxy locations and combiner circuitry for combining the toggle data in a first time window with a set of weight value to produce a measure of power usage in the first circuit. The proxy locations and weight values are selected automatically based on simulated or emulated signals from a larger set of locations in the first circuit and associated power usage in the first circuit.

公开(公告)号：US20220163576A1

公开(公告)日：2022-05-26

申请号：US17218686

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Zhiyao Xie ,  Shidhartha Das

IPC: G01R21/133 ,  G06F30/3308

Abstract: An integrated circuit includes a first circuit and a power meter coupled to the first circuit at selected proxy locations. The power meter includes circuitry for generating toggle data, such as signal transitions or signal levels, from signals at the proxy locations and combiner circuitry for combining the toggle data in a first time window with a set of weight value to produce a measure of power usage in the first circuit. The proxy locations and weight values are selected automatically based on simulated or emulated signals from a larger set of locations in the first circuit and associated power usage in the first circuit.

公开(公告)号：US20220130816A1

公开(公告)日：2022-04-28

申请号：US17077532

申请日：2020-10-22

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Mudit Bhargava ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha

IPC: H01L27/02 ,  H01L25/065 ,  H01L23/535 ,  H01L21/768 ,  H01L25/00 ,  G06F30/31

Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.

公开(公告)号：US11295053B2

公开(公告)日：2022-04-05

申请号：US16569482

申请日：2019-09-12

Applicant: Arm Limited

Inventor： Xiaoqing Xu ,  Brian Tracy Cline ,  Saurabh Pijuskumar Sinha ,  Stephen Lewis Moore ,  Mudit Bhargava

IPC: G06F30/394 ,  G06F30/392 ,  G06F30/327 ,  G06F111/20

Abstract: Various implementations described herein are directed to an integrated circuit (IC) having a design that is severable into multiple sub-circuits having input-output (IO) ports. The integrated circuit (IC) may include multiple physical electrical connections that are adapted to electrically interconnect the IO ports of the multiple sub-circuits to operate as the IC, and the IO ports have three-dimensional (3D) geometric position information associated therewith.

公开(公告)号：US10825745B1

公开(公告)日：2020-11-03

申请号：US16666816

申请日：2019-10-29

Applicant: Arm Limited

Inventor： Saurabh Pijuskumar Sinha ,  Xiaoqing Xu ,  Joel Thornton Irby ,  Mudit Bhargava

IPC: H01L21/66 ,  H01L25/18 ,  G06F30/30 ,  G06F30/333

Abstract: A multi-die integrated circuit with improved testability can include at least two dies that combined comprise an integrated circuit for a self-contained system, which includes logic and design-for-test features. The integrated circuit is split into at least two portions, where each portion is disposed on a corresponding one of the at least two dies. As part of the improved testability for both pre-bond testing of logic and post-bond testing of inter-die connections, at least one of the at least two dies further comprises a split-circuit-boundary scan chain. An automated design tool can be used to determine optimal ways for the integrated circuit for a self-contained system to be split into at least two portions for the corresponding at least two dies. In addition, a split-circuit-boundary scan chain option can be applied for each portion, via the automated design tool, to ensure boundary scans are available on timing paths.

公开(公告)号：US20190026417A1

公开(公告)日：2019-01-24

申请号：US16140461

申请日：2018-09-24

Applicant: Arm Limited

Inventor： Paul de Dood ,  Marlin Wayne Frederick, JR. ,  Jerry Chaoyuan Wang ,  Brian Tracy Cline ,  Xiaoqing Xu ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Tom Shore ,  Sriram Thyagarajan ,  Gus Yeung ,  Daniel J. Albers ,  David William Granda

IPC: G06F17/50

Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell. Such an approach enables both the schematic and layout to be co-optimised during generation of the layout of the cell.