公开(公告)号：US20240363601A1

公开(公告)日：2024-10-31

申请号：US18646794

申请日：2024-04-26

申请人： STATS CHIPPAC SEMICONDUCTOR (JIANGYIN) CO., LTD.

发明人： Zelong Yu ,  Huanhuan Yuan ,  Jian Xu ,  Soo Won Lee

IPC分类号： H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

CPC分类号： H01L25/105 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125

摘要： The present disclosure discloses a chip package structure and a preparation method thereof. The chip package structure includes: a metal wiring layer; a first chip, wherein a front surface of the first chip is flip-chipped on a first surface of the metal wiring layer; a first molding layer coating the first chip; a second chip, wherein a front surface of the second chip is flip-chipped on a second surface of the metal wiring layer; a first metal pillar formed on the second surface of the metal wiring layer; a second molding layer coating the second chip and the first metal pillar; and a second metal pillar formed on one side that is of the second molding layer and that is far away from the metal wiring layer, wherein the second metal pillar is at least partially connected to the corresponding first metal pillar.

公开(公告)号：US20240363593A1

公开(公告)日：2024-10-31

申请号：US18767883

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Wen-Chih Chiou

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L21/822 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532 ,  H01L23/538 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L21/8221 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/53295 ,  H01L23/5384 ,  H01L24/32 ,  H01L25/50 ,  H01L2224/0401

摘要： A semiconductor device including a first integrated circuit component, a second integrated circuit component, a third integrated circuit component, and a dielectric encapsulation is provided. The second integrated circuit component is stacked on and electrically coupled to the first integrated circuit component, and the third integrated circuit component is stacked on and electrically coupled to the second integrated circuit component. The dielectric encapsulation is disposed on the second integrated circuit component and laterally encapsulating the third integrated circuit component, where outer sidewalls of the dielectric encapsulation are substantially aligned with sidewalls of the first and second integrated circuit components. A manufacturing method of the above-mentioned semiconductor device is also provided.

公开(公告)号：US20240363533A1

公开(公告)日：2024-10-31

申请号：US18769153

申请日：2024-07-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Hao TSAI ,  Techi WONG ,  Meng-Liang LIN ,  Yi-Wen WU ,  Po-Yao CHUANG ,  Shin-Puu JENG

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/07

CPC分类号： H01L23/5283 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49575 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/17 ,  H01L24/32 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/3207 ,  H01L2224/32225 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2924/1436 ,  H01L2924/1437

摘要： A package structure is provided. The package structure includes a first interconnect structure, a die structure over the first interconnect structure, and a dam structure on the die structure. The package structure also includes a second interconnect structure over the die structure and the dam structure. The package structure further includes a ring structure over the first interconnect structure and surrounding the die structure and the dam structure. In addition, the package structure includes a plurality of connectors electrically connected to the first interconnect structure and the second interconnect structure. A top surface of the ring structure is higher than a top surface of the first interconnect structure and lower than a top surface of each of the plurality of connectors.

公开(公告)号：US20240363398A1

公开(公告)日：2024-10-31

申请号：US18765006

申请日：2024-07-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Sheng TANG ,  Fu-Chen CHANG ,  Cheng-Lin HUANG ,  Wen-Ming CHEN ,  Chun-Yen LO ,  Kuo-Chio LIU

IPC分类号： H01L21/768 ,  H01L21/304 ,  H01L21/67 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/58 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L21/76802 ,  H01L21/304 ,  H01L21/3043 ,  H01L21/67011 ,  H01L21/67092 ,  H01L21/67132 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/48 ,  H01L23/481 ,  H01L24/11 ,  H01L24/32 ,  H01L23/49816 ,  H01L23/562 ,  H01L23/585 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

摘要： A semiconductor die is provided. The semiconductor die includes a substrate having a front surface, a rear surface opposite to the front surface, and a sidewall connected between the front surface and the rear surface. The sidewall includes a first primary segment immediately connected to the front surface, a second primary segment immediately connected to the rear surface, and a middle segment between the first primary segment and the second primary segment. The slope of the second primary segment is less than the slope of the first primary segment, and the slope of the middle segment is less than the slope of the second primary segment. Each of the first primary segment, the second primary segment, and the middle segment is a flat surface having a slope greater than 0 degrees relative to a line parallel to the front surface of the substrate.

公开(公告)号：US12132029B2

公开(公告)日：2024-10-29

申请号：US17648161

申请日：2022-01-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Chia Hu ,  Ming-Fa Chen

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/552 ,  H01L25/00 ,  H01L25/03 ,  H01L25/18

CPC分类号： H01L25/0657 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/08 ,  H01L24/19 ,  H01L24/80 ,  H01L24/94 ,  H01L25/03 ,  H01L25/50 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/08145 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/73259 ,  H01L2224/80895 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/3025 ,  H01L2224/94 ,  H01L2224/80

摘要： A method includes bonding a first device die with a second device die. The second device die is over the first device die. A passive device is formed in a combined structure including the first and the second device dies. The passive device includes a first and a second end. A gap-filling material is formed over the first device die, with the gap-filling material including portions on opposite sides of the second device die. The method further includes performing a planarization to reveal the second device die, with a remaining portion of the gap-filling material forming an isolation region, forming a first and a second through-vias penetrating through the isolation region to electrically couple to the first device die, and forming a first and a second electrical connectors electrically coupling to the first end and the second end of the passive device.

公开(公告)号：US12131984B2

公开(公告)日：2024-10-29

申请号：US18302112

申请日：2023-04-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Po-Hao Tsai ,  Po-Yao Chuang ,  Shin-Puu Jeng ,  Techi Wong

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/49822 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/18 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/181 ,  H01L2924/00012

摘要： A semiconductor device and method of manufacture are provided whereby an interposer and a first semiconductor device are placed onto a carrier substrate and encapsulated. The interposer comprises a first portion and conductive pillars extending away from the first portion. A redistribution layer located on a first side of the encapsulant electrically connects the conductive pillars to the first semiconductor device.

公开(公告)号：US20240355744A1

公开(公告)日：2024-10-24

申请号：US18758040

申请日：2024-06-28

申请人： Amkor Technology Singapore Holding Pte. Ltd.

发明人： Ji Young Chung ,  Seung Chul Jang ,  Ron Huemoeller

IPC分类号： H01L23/538 ,  H01L23/552 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L23/552 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06586

摘要： In one example, an electronic assembly comprises a first semiconductor device and a second semiconductor device. Each of the first semiconductor device and the second semiconductor devices comprises a substrate comprising a top surface and a conductive structure, an electronic component over the top surface of the substrate, a dielectric material over the top surface of the substrate and contacting a side of the electronic component, a substrate tab at an end of substrate and not covered by the dielectric material, wherein the conductive structure of the substrate is exposed at the substrate tab, and an interconnect electrically coupled to the conductive structure at the substrate tab of the first semiconductor device and the conductive structure at the substrate tab of the second semiconductor device. Other examples and related methods are also disclosed herein.

公开(公告)号：US12127406B2

公开(公告)日：2024-10-22

申请号：US17577533

申请日：2022-01-18

申请人： SANDISK TECHNOLOGIES LLC

发明人： Takaaki Iwai ,  Takashi Inomata ,  Takayuki Maekura

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L23/535 ,  H01L25/00 ,  H01L25/065 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B51/20 ,  H10B51/30 ,  H10B63/00

CPC分类号： H10B43/27 ,  H01L23/535 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B51/20 ,  H10B51/30 ,  H10B63/34 ,  H10B63/845 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1441 ,  H01L2924/1444 ,  H01L2924/14511

摘要： A semiconductor structure includes an alternating stack of insulating layers and composite layers. Each of the composite layers includes a plurality of electrically conductive word line strips laterally extending along a first horizontal direction and a plurality of dielectric isolation strips laterally extending along the first horizontal direction and interlaced with the plurality of electrically conductive word line strips. Rows of memory openings are arranged along the first horizontal direction. Each row of memory openings vertically extends through each insulating layer within the alternating stack and one electrically conductive strip for each of the composite layers. Rows of memory opening fill structures are located within the rows of memory openings. Each of the memory opening fill structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel.

公开(公告)号：US12125833B2

公开(公告)日：2024-10-22

申请号：US18346319

申请日：2023-07-03

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shin-Puu Jeng ,  Shuo-Mao Chen ,  Feng-Cheng Hsu

IPC分类号： H01L25/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L25/16 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5384 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06586 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19105

摘要： A method includes bonding a first package component and a second package component to an interposer. The first package component includes a core device die, and the second package component includes a memory die. An Independent Passive Device (IPD) die is bonded directly to the interposer. The IPD die is electrically connected to the first package component through a first conductive path in the interposer. A package substrate is bonded to the interposer die. The package substrate is on an opposing side of the interposer than the first package component and the second package component.

公开(公告)号：US12125821B2

公开(公告)日：2024-10-22

申请号：US18080661

申请日：2022-12-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Fa Chen ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00

CPC分类号： H01L25/0652 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/97 ,  H01L25/50 ,  H01L2225/06541

摘要： A package includes an integrated circuit. The integrated circuit includes a first chip, a dummy chip, a second chip, and a third chip. The first chip includes a semiconductor substrate that extends continuously from an edge of the first chip to another edge of the first chip. The dummy chip is disposed over the first chip and includes a semiconductor substrate that extends continuously from an edge of the dummy chip to another edge of the dummy chip. Sidewalls of the first chip are aligned with sidewalls of the dummy chip. The second chip and the third chip are sandwiched between the first chip and the dummy chip. A thickness of the second chip is substantially equal to a thickness of the third chip.