公开(公告)号：US09116844B2

公开(公告)日：2015-08-25

申请号：US14246162

申请日：2014-04-07

Applicant: ARM Limited

Inventor： Emre Ozer ,  Yiannakis Sazeides ,  Daniel Kershaw ,  Stuart David Biles

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/07

CPC classification number: G06F11/1415 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/0787 ,  G06F2201/86

Abstract: A data processing apparatus has a plurality of storage elements residing at different physical locations within the apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry monitors the global transient fault history data to determine, based on predetermined criteria, whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack. This provides a simple and effective mechanism for distinguishing between random transient faults that may naturally occur, and a coordinated transient fault attack that may be initiated in an attempt to circumvent the security of the data processing apparatus.

Abstract translation: 数据处理装置具有驻留在装置内的不同物理位置的多个存储元件，以及故障历史电路，用于检测每个存储元件中发生的局部瞬态故障，并且用于基于检测到的局部瞬态故障来维护全局瞬态故障历史数据。 分析电路监视全局瞬态故障历史数据，以基于预定标准确定全局瞬态故障历史数据是否表示在数据处理装置内发生的随机瞬态故障，或指示协调的瞬时故障攻击。 分析电路然后被配置为启动对协调的瞬态故障攻击的确定的对策动作。 这提供了一种用于区分可能自然发生的随机瞬态故障的简单和有效的机制，以及可以在试图绕过数据处理设备的安全性时发起的协调的瞬态故障攻击。