公开(公告)号：US20230111938A1

公开(公告)日：2023-04-13

申请号：US17956751

申请日：2022-09-29

申请人： ARTERIS, INC.

发明人： Benoit LAFAGE ,  Insaf MELIANE ,  Cyril HABERT ,  Gregoire AVOT

IPC分类号： G01R31/319 ,  G01R31/317 ,  G01R31/302

摘要： A system and method are disclosed for assembling a testbench for evaluating electronic systems. The method includes assembling large testbenches by using verification features associated with functional components, automatically creating component connections, and statistically checking the testbench prior to generation and simulation. The system includes a computer system that implements the method.

公开(公告)号：US20230025288A1

公开(公告)日：2023-01-26

申请号：US17855806

申请日：2022-07-01

申请人： ARTERIS, INC.

发明人： Benoit LAFAGE ,  Insaf MELIANE ,  Nabil GUISSOUMA

IPC分类号： G06F30/398 ,  G06F30/394 ,  G06F11/32

摘要： In accordance with various embodiments and aspects of the invention, systems and methods are disclosed that create a system-level address map and create a report. A system description of an electronic system (e.g., integrated circuit (IC)) is received that includes configuration parameters. A tree representation of the system is created based on the interconnect of the system. Each port of the system is assigned a tree node. To create a corresponding system-level address map, the tree representation is traversed from target(s) to initiator(s), calculating the address transformation at each node. A report of the system-level address map is created, and defects such as address duplication, missing addresses, etc. can be identified and reported to the user.