公开(公告)号：US10438951B2

公开(公告)日：2019-10-08

申请号：US15921056

申请日：2018-03-14

Applicant: ASAHI KASEI MICRODEVICES CORPORATION

Inventor： Shuntaro Fujii ,  Tatsushi Yagi ,  Shohei Hamada

IPC: H01L27/092 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/266 ,  H01L29/06 ,  H01L21/8238

Abstract: An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that may achieve low power consumption in a digital circuit and reduce influence of noise in an analog circuit. The manufacturing method of the semiconductor device includes a first source/drain forming step of forming a first source region and a first drain region by implanting impurities of a second conductivity type into a digital side second conductivity type impurity layer using a gate electrode and a sidewall as a mask and a second drain/source forming step of forming a second source region and a second drain region by implanting impurities of the second conductivity type into an analog side second conductivity type impurity layer using a gate electrode and a sidewall as a mask more shallowly than the impurities of the second conductivity type implanted in the first source/drain forming step.