公开(公告)号：US10446645B2

公开(公告)日：2019-10-15

申请号：US15913139

申请日：2018-03-06

Applicant: ASAHI KASEI MICRODEVICES CORPORATION

Inventor： Shuntaro Fujii

IPC: H01L21/28 ,  H01L21/74 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/265 ,  H01L21/285 ,  H01L21/324 ,  H01L29/167 ,  H01L29/423

Abstract: A semiconductor device 1 includes: a well region 5 provided on a surface layer of a semiconductor substrate 2; a source region 14S and a drain region 15D disposed to be distant from each other on the surface layer of the well region 5; a channel region 6 provided between the source region 14S and the drain region 15D; and a gate electrode 8 provided over the channel region 6 with a gate insulator 7 interposed therebetween. A gate length of the gate electrode 8 is 1.5 μm or less, the channel region 6 includes indium as a channel impurity, a distance between a surface of the channel region 6 and a concentration peak position of the channel impurity is 20 nm to 70 nm, and a concentration of the channel impurity gradually decreases in a direction from the concentration peak position of the channel impurity to the surface of the channel region.

公开(公告)号：US10438951B2

公开(公告)日：2019-10-08

申请号：US15921056

申请日：2018-03-14

Applicant: ASAHI KASEI MICRODEVICES CORPORATION

Inventor： Shuntaro Fujii ,  Tatsushi Yagi ,  Shohei Hamada

IPC: H01L27/092 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/266 ,  H01L29/06 ,  H01L21/8238

Abstract: An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that may achieve low power consumption in a digital circuit and reduce influence of noise in an analog circuit. The manufacturing method of the semiconductor device includes a first source/drain forming step of forming a first source region and a first drain region by implanting impurities of a second conductivity type into a digital side second conductivity type impurity layer using a gate electrode and a sidewall as a mask and a second drain/source forming step of forming a second source region and a second drain region by implanting impurities of the second conductivity type into an analog side second conductivity type impurity layer using a gate electrode and a sidewall as a mask more shallowly than the impurities of the second conductivity type implanted in the first source/drain forming step.

公开(公告)号：US11462625B2

公开(公告)日：2022-10-04

申请号：US17172165

申请日：2021-02-10

Applicant: ASAHI KASEI MICRODEVICES CORPORATION

Inventor： Shuntaro Fujii

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/225

Abstract: The semiconductor device includes a well region disposed in a surface layer of a semiconductor substrate, a source region and a drain region arranged separated from each other in a surface layer of the well region, a channel region disposed between the source region and the drain region, and a gate electrode disposed on the channel region via a gate insulating film containing fluorine, in which concentration of fluorine existing in a first interface, the first interface being an interface of the gate insulating film with the gate electrode, and concentration of fluorine existing in a second interface, the second interface being an interface of the gate insulating film with the channel region, are higher than concentration of fluorine existing in a middle region in the depth direction of the gate insulating film, and fluorine concentration in the first interface is higher than fluorine concentration in the second interface.

公开(公告)号：US20180286950A1

公开(公告)日：2018-10-04

申请号：US15913139

申请日：2018-03-06

Applicant: ASAHI KASEI MICRODEVICES CORPORATION

Inventor： Shuntaro Fujii

IPC: H01L29/10 ,  H01L29/167 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/74 ,  H01L21/265 ,  H01L21/324 ,  H01L21/225 ,  H01L21/28 ,  H01L21/285

CPC classification number: H01L29/1041 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/74 ,  H01L29/1083 ,  H01L29/167 ,  H01L29/42376 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/7833

Abstract: To reduce a 1/f noise of an insulated gate field effect transistor.A semiconductor device 1 includes: a well region 5 provided on a surface layer of a semiconductor substrate 2; a source region 14S and a drain region 15D disposed to be distant from each other on the surface layer of the well region 5; a channel region 6 provided between the source region 14S and the drain region 15D; and a gate electrode 8 provided over the channel region 6 with a gate insulator 7 interposed therebetween. A gate length of the gate electrode 8 is 1.5 μm or less, the channel region 6 includes indium as a channel impurity, a distance between a surface of the channel region 6 and a concentration peak position of the channel impurity is 20 nm to 70 nm, and a concentration of the channel impurity gradually decreases in a direction from the concentration peak position of the channel impurity to the surface of the channel region.