公开(公告)号：US10664403B1

公开(公告)日：2020-05-26

申请号：US16200585

申请日：2018-11-26

申请人： ATI Technologies ULC

发明人： Leon King Nok Lai ,  Qian Ma ,  Jimshed B. Mirza

IPC分类号： G06F12/08 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0871

摘要： A technique for prefetching data for a cache is provided. The technique includes detecting access to a data block. In response to the detection, a prefetch block generates proposed blocks for prefetch. The prefetch block also examines prefetch tracking data to determine whether a prefetch group including the proposed blocks is marked as already having been prefetched. If the group has been marked as already having been prefetched, then prefetch block does not prefetch that data, thereby avoiding traffic between the prefetch block and the cache memory. Using this technique, unnecessary requests to prefetch data into the cache memory are avoided.

公开(公告)号：US20180246820A1

公开(公告)日：2018-08-30

申请号：US15442402

申请日：2017-02-24

申请人： ATI Technologies ULC

发明人： Jimshed Mirza ,  Qian Ma

IPC分类号： G06F13/16

摘要： A system and method for maintaining information of pending operations are described. A buffer uses multiple linked lists implementing a single logical queue for a single requestor. The buffer maintains multiple head pointers and multiple tail pointers for the single requestor. Data entries of the single logical queue are stored in an alternating pattern among the multiple linked lists. During the allocation of buffer entries, the tail pointers are selected in the same alternating manner, and during the deallocation of buffer entries, the multiple head pointers are selected in the same manner.

公开(公告)号：US20200159664A1

公开(公告)日：2020-05-21

申请号：US16195435

申请日：2018-11-19

申请人： ATI Technologies ULC

发明人： Leon King Nok Lai ,  Qian Ma ,  Jimshed B. Mirza

IPC分类号： G06F12/0891 ,  G06F3/06

摘要： A technique for improving performance of a cache is provided. The technique involves maintaining indicators of whether cache entries are dirty in a random access memory (“RAM”) that has a lower latency to a cache controller than the cache memory that stores the cache entries. When a request to invalidate one or more cache entries is received by the cache controller, the cache controller checks the RAM to determine whether any cache entries are dirty and thus should be written out to a backing store. Using the RAM removes the need to check the actual cache memory for whether cache entries are dirty, which reduces the latency associated with performing such checks and thus with performing cache invalidations.

公开(公告)号：US10545887B2

公开(公告)日：2020-01-28

申请号：US15442402

申请日：2017-02-24

申请人： ATI Technologies ULC

发明人： Jimshed Mirza ,  Qian Ma

IPC分类号： G06F13/16

摘要： A system and method for maintaining information of pending operations are described. A buffer uses multiple linked lists implementing a single logical queue for a single requestor. The buffer maintains multiple head pointers and multiple tail pointers for the single requestor. Data entries of the single logical queue are stored in an alternating pattern among the multiple linked lists. During the allocation of buffer entries, the tail pointers are selected in the same alternating manner, and during the deallocation of buffer entries, the multiple head pointers are selected in the same manner.

公开(公告)号：US20200159581A1

公开(公告)日：2020-05-21

申请号：US16195412

申请日：2018-11-19

申请人： ATI Technologies ULC

发明人： Jimshed B. Mirza ,  Qian Ma ,  Leon King Nok Lai

IPC分类号： G06F9/50

摘要： A technique for scheduling processing tasks having different latencies is provided. The technique involves identifying one or more available requests in a request queue, where each request queue corresponds to a different latency. A request arbiter examines a shift register to determine whether there is an available slot for the one or more requests. A slot is available for a request if there is a slot that is a number of slots from the end of the shift register equal to the number of cycles the request takes to complete processing in a corresponding processing pipeline. If a slot is available, the request is scheduled for execution and the slot is marked as being occupied. If a slot is not available, the request is not scheduled for execution on the current cycle. On transitioning to a new cycle, the shift register is shifted towards its end and the technique repeats.

公开(公告)号：US20200167287A1

公开(公告)日：2020-05-28

申请号：US16200585

申请日：2018-11-26

申请人： ATI Technologies ULC

发明人： Leon King Nok Lai ,  Qian Ma ,  Jimshed B. Mirza

IPC分类号： G06F12/0862 ,  G06F12/0871 ,  G06F12/0875

摘要： A technique for prefetching data for a cache is provided. The technique includes detecting access to a data block. In response to the detection, a prefetch block generates proposed blocks for prefetch. The prefetch block also examines prefetch tracking data to determine whether a prefetch group including the proposed blocks is marked as already having been prefetched. If the group has been marked as already having been prefetched, then then prefetch block does not prefetch that data, thereby avoiding traffic between the prefetch block and the cache memory. Using this technique, unnecessary requests to prefetch data into the cache memory are avoided.

公开(公告)号：US20200167076A1

公开(公告)日：2020-05-28

申请号：US16200573

申请日：2018-11-26

申请人： ATI Technologies ULC

发明人： Leon King Nok Lai ,  Qian Ma ,  Jimshed B. Mirza

IPC分类号： G06F3/06 ,  G06F12/0875 ,  G06F9/38

摘要： A technique for improving performance of a data compression system is provided. The technique is applicable to compressed data sets that include compression blocks. Each compression block may be either compressed or uncompressed. Metadata indicating whether compression blocks are actually compressed or not is stored. If compression blocks are not compressed, then a read-decompress-modify-compress-write pipeline is bypassed. Instead, a compression unit writes the data specified by the partial request into the compression block, without reading, decompressing, modifying, recompressing, and writing the data, resulting in a much faster operation.

公开(公告)号：US10956338B2

公开(公告)日：2021-03-23

申请号：US16195435

申请日：2018-11-19

申请人： ATI Technologies ULC

发明人： Leon King Nok Lai ,  Qian Ma ,  Jimshed B. Mirza

IPC分类号： G06F12/0891 ,  G06F3/06

摘要： A technique for improving performance of a cache is provided. The technique involves maintaining indicators of whether cache entries are dirty in a random access memory (“RAM”) that has a lower latency to a cache controller than the cache memory that stores the cache entries. When a request to invalidate one or more cache entries is received by the cache controller, the cache controller checks the RAM to determine whether any cache entries are dirty and thus should be written out to a backing store. Using the RAM removes the need to check the actual cache memory for whether cache entries are dirty, which reduces the latency associated with performing such checks and thus with performing cache invalidations.

公开(公告)号：US10915359B2

公开(公告)日：2021-02-09

申请号：US16195412

申请日：2018-11-19

申请人： ATI Technologies ULC

发明人： Jimshed B. Mirza ,  Qian Ma ,  Leon King Nok Lai

IPC分类号： G06F9/50

摘要： A technique for scheduling processing tasks having different latencies is provided. The technique involves identifying one or more available requests in a request queue, where each request queue corresponds to a different latency. A request arbiter examines a shift register to determine whether there is an available slot for the one or more requests. A slot is available for a request if there is a slot that is a number of slots from the end of the shift register equal to the number of cycles the request takes to complete processing in a corresponding processing pipeline. If a slot is available, the request is scheduled for execution and the slot is marked as being occupied. If a slot is not available, the request is not scheduled for execution on the current cycle. On transitioning to a new cycle, the shift register is shifted towards its end and the technique repeats.