公开(公告)号：US20150154735A1

公开(公告)日：2015-06-04

申请号：US14556801

申请日：2014-12-01

Applicant: ATI Technologies ULC

Inventor： Milivoje Aleksic ,  Raymond M. Li ,  Danny H.M. Cheng ,  Carl K. Mizuyabu ,  Antonio Asaro

IPC: G06T1/60 ,  G06F13/28 ,  G06T1/20 ,  G06F13/16

CPC classification number: G06T1/60 ,  G06F13/1663 ,  G06F13/1684 ,  G06F13/28 ,  G06T1/20 ,  G09G5/39 ,  G09G5/393 ,  G09G2360/125

Abstract: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.

Abstract translation: 中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中，两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。

公开(公告)号：US20170301058A1

公开(公告)日：2017-10-19

申请号：US15638868

申请日：2017-06-30

Applicant: ATI Technologies ULC

Inventor： Milivoje Aleksic ,  Raymond M. Li ,  Danny H.M. Cheng ,  Carl K. Mizuyabu ,  Anthony Asaro

IPC: G06T1/60 ,  G06F13/16 ,  G06F13/28 ,  G06T1/20 ,  G09G5/39 ,  G09G5/393

CPC classification number: G06T1/60 ,  G06F13/1663 ,  G06F13/1684 ,  G06F13/28 ,  G06T1/20 ,  G09G5/39 ,  G09G5/393 ,  G09G2360/125

Abstract: An apparatus includes a unified system/graphics memory and a memory controller. The memory controller is operative to receive client data access requests associated with one or more clients and a central processing unit (CPU) data access request associated with a CPU, to a plurality of memory channels for accessing the unified system/graphics memory. The memory controller is operative to provide access to the plurality of memory channels, in parallel, by the CPU and at least one client of the one or more clients. The memory controller is operative to prioritize the CPU data access request to the unified memory over the client data access requests to the unified memory and control the plurality of memory channels to access, in parallel, data for the CPU and data for the at least one client based on a request of the client data access requests and the CPU data access request.

公开(公告)号：US09734549B2

公开(公告)日：2017-08-15

申请号：US14556801

申请日：2014-12-01

Applicant: ATI Technologies ULC

Inventor： Milivoje Aleksic ,  Raymond M. Li ,  Danny H. M. Cheng ,  Carl K. Mizuyabu ,  Anthony Asaro

IPC: G06F13/14 ,  G06T1/60 ,  G09G5/39 ,  G06F13/16 ,  G06F13/28 ,  G06T1/20 ,  G09G5/393

CPC classification number: G06T1/60 ,  G06F13/1663 ,  G06F13/1684 ,  G06F13/28 ,  G06T1/20 ,  G09G5/39 ,  G09G5/393 ,  G09G2360/125

Abstract: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.

公开(公告)号：US09959593B2

公开(公告)日：2018-05-01

申请号：US15638868

申请日：2017-06-30

Applicant: ATI Technologies ULC

Inventor： Milivoje Aleksic ,  Raymond M. Li ,  Danny H. M. Cheng ,  Carl K. Mizuyabu ,  Anthony Asaro

IPC: G06F13/14 ,  G06T1/60 ,  G09G5/39 ,  G06F13/16 ,  G06F13/28 ,  G06T1/20 ,  G09G5/393

CPC classification number: G06T1/60 ,  G06F13/1663 ,  G06F13/1684 ,  G06F13/28 ,  G06T1/20 ,  G09G5/39 ,  G09G5/393 ,  G09G2360/125

Abstract: An apparatus includes a unified system/graphics memory and a memory controller. The memory controller is operative to receive client data access requests associated with one or more clients and a central processing unit (CPU) data access request associated with a CPU, to a plurality of memory channels for accessing the unified system/graphics memory. The memory controller is operative to provide access to the plurality of memory channels, in parallel, by the CPU and at least one client of the one or more clients. The memory controller is operative to prioritize the CPU data access request to the unified memory over the client data access requests to the unified memory and control the plurality of memory channels to access, in parallel, data for the CPU and data for the at least one client based on a request of the client data access requests and the CPU data access request.