公开(公告)号：US20200161426A1

公开(公告)日：2020-05-21

申请号：US16192897

申请日：2018-11-16

申请人： ATOMERA INCORPORATED

发明人： DANIEL CONNELLY ,  Marek Hytha ,  Hideki Takeuchi ,  Richard Burton ,  Robert J. Mears

IPC分类号： H01L29/15 ,  H01L29/417 ,  H01L29/08 ,  H01L29/45 ,  H01L29/16 ,  H01L29/36 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

摘要： A semiconductor device may include a semiconductor layer and at least one contact in the semiconductor layer. The contact may include at least one oxygen monolayer constrained within a crystal lattice of adjacent semiconductor portions of the semiconductor layer and spaced apart from a surface of the semiconductor layer by between one and four monolayers, and a metal layer on the surface of the semiconductor layer above the at least one oxygen monolayer. The semiconductor portion between the oxygen monolayer and the metal layer may have a dopant concentration of 1×1021 atoms/cm3 or greater.

公开(公告)号：US20200161429A1

公开(公告)日：2020-05-21

申请号：US16192987

申请日：2018-11-16

申请人： ATOMERA INCORPORATED

发明人： HIDEKI TAKEUCHI ,  DANIEL CONNELLY ,  MAREK HYTHA ,  RICHARD BURTON ,  ROBERT J. MEARS

IPC分类号： H01L29/15 ,  H01L29/08 ,  H01L29/66 ,  H01L29/165 ,  H01L21/265 ,  H01L29/167 ,  H01L21/225

摘要： A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.

公开(公告)号：US20220285498A1

公开(公告)日：2022-09-08

申请号：US17750683

申请日：2022-05-23

申请人： ATOMERA INCORPORATED

发明人： ROBERT JOHN STEPHENSON ,  RICHARD BURTON ,  DMITRI CHOUTOV ,  NYLES WYNN CODY ,  DANIEL CONNELLY ,  ROBERT J. MEARS ,  ERWIN TRAUTMANN

IPC分类号： H01L29/15 ,  H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L23/485

摘要： A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice layer extending vertically adjacent the at least one trench. The superlattice layer may comprise stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer. Each at least one non-semiconductor monolayer of each group of layers may be constrained within a crystal lattice of adjacent base semiconductor portions. The vertical semiconductor device may also include a doped semiconductor layer adjacent the superlattice layer, and a conductive body adjacent the doped semiconductor layer on a side thereof opposite the superlattice layer and defining a vertical semiconductor device contact.

公开(公告)号：US20210074814A1

公开(公告)日：2021-03-11

申请号：US17101399

申请日：2020-11-23

申请人： ATOMERA INCORPORATED

发明人： ROBERT JOHN STEPHENSON ,  RICHARD BURTON ,  DMITRI CHOUTOV ,  NYLES WYNN CODY ,  DANIEL CONNELLY ,  ROBERT J. MEARS ,  ERWIN TRAUTMANN

IPC分类号： H01L29/15 ,  H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L23/485

摘要： A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner. The superlattice liner may include a plurality of stacked groups of layers, each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group being constrained within a crystal lattice of adjacent base semiconductor portions. The device may also include a semiconductor layer on the superlattice liner and including a dopant constrained therein by the superlattice liner, and a conductive body within the at least one trench defining a source contact.

公开(公告)号：US20200161427A1

公开(公告)日：2020-05-21

申请号：US16192911

申请日：2018-11-16

申请人： ATOMERA INCORPORATED

发明人： HIDEKI TAKEUCHI ,  DANIEL CONNELLY ,  MAREK HYTHA ,  RICHARD BURTON ,  ROBERT J. MEARS

IPC分类号： H01L29/15 ,  H01L21/283 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225

摘要： A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The method may further include forming a gate on the channel region, depositing at least one metal layer on the upper region, and applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.

公开(公告)号：US20190280090A1

公开(公告)日：2019-09-12

申请号：US16296414

申请日：2019-03-08

申请人： ATOMERA INCORPORATED

发明人： ROBERT JOHN STEPHENSON ,  RICHARD BURTON ,  DMITRI CHOUTOV ,  NYLES WYNN CODY ,  DANIEL CONNELLY ,  ROBERT J, MEARS ,  ERWIN TRAUTMANN

IPC分类号： H01L29/15 ,  H01L29/417 ,  H01L29/08 ,  H01L29/45 ,  H01L21/285

摘要： A semiconductor device may include a semiconductor substrate having a trench therein, and a superlattice liner at least partially covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and a conductive body within the trench.