公开(公告)号：US20170154567A1

公开(公告)日：2017-06-01

申请号：US15357331

申请日：2016-11-21

Applicant: AU Optronics Corporation

Inventor： Chien-Chuan KO ,  Chun-Hung KUO ,  Meng-Chieh TSAI

IPC: G09G3/20 ,  G06F3/041 ,  G11C19/28

CPC classification number: G09G3/2092 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/044 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2354/00 ,  G11C19/28

Abstract: A display driving method includes: performing a display scan function and a display stop function during a plurality of frame periods; during one frame period, outputting, alternately and sequentially along a scan direction, N scan signals according to K clock signals when performing the display scan function, wherein each of the scan signals has an enable period of a scan line, the clock signals sequentially have a delay, and each of the clock signals is a periodic signal with K delays as one period; providing a driving control signal and disabling the clock signals when performing the display stop function during a display stop period, wherein an initiation time position of the display stop period is changed based on an offset between two neighboring frame periods, and the neighboring frame periods have no overlapping or interlacing interval.

公开(公告)号：US20210248944A1

公开(公告)日：2021-08-12

申请号：US17094849

申请日：2020-11-11

Applicant: AU Optronics Corporation

Inventor： Yu-Jen CHEN ,  Meng-Chieh TSAI

IPC: G09G3/20 ,  G11C19/28

Abstract: A gate driving circuit includes a plurality of shift registers coupled in series. An nth shift register includes a driving circuit and a pull-down circuit. The driving circuit is electrically coupled to an output node and a first node. The driving circuit is configured to receive a first clock signal and output a gate signal according to the first clock signal. The pull-down circuit is electrically coupled to the output node. The pull-down circuit is configured to receive an (n−m)th gate signal and an (n+m)th gate signal, and pull-down the gate signal to a low voltage level according to one of the (n−m)th gate signal and the (n+m)th gate signal, wherein m and n are positive integers.

公开(公告)号：US20200160771A1

公开(公告)日：2020-05-21

申请号：US16684664

申请日：2019-11-15

Applicant: AU OPTRONICS CORPORATION

Inventor： Wei-Chien LIAO ,  Yu-Jen CHEN ,  Meng-Chieh TSAI

IPC: G09G3/20 ,  H01L27/12

Abstract: A display device includes a plurality of pixel electrodes arranged in an array. A first switch electrically connected to a first pixel electrode of the pixel electrodes. A second switch electrically connected to a second pixel electrode of the pixel electrodes. The second switch is electrically connected between the first switch and a data line, and the first pixel electrode and the first pixel electrode are respectively located at two row of the pixel electrodes that are not adjacent to each other.

公开(公告)号：US20190130808A1

公开(公告)日：2019-05-02

申请号：US16168937

申请日：2018-10-24

Applicant: AU Optronics Corporation

Inventor： Chien-Chuan KO ,  Meng-Chieh TSAI

IPC: G09G3/20

Abstract: A scan driver that includes a plurality of stages of scan driving circuits is provided. Each scan driving circuit includes: a driving transistor, including: a control terminal configured to receive a current-stage scan control signal, a first terminal configured to receive a first clock signal, and a second terminal configured to output a current-stage scan signal; an input stage circuit coupled to the driving transistor, where the input stage circuit includes: a first input transistor and a second input transistor, the first input transistor includes: a control terminal, a first terminal, and a second terminal, the second input transistor includes: a control terminal, a first terminal, and a second terminal, the control terminal of the first input transistor is configured to receive a next-stage scan signal, the control terminal of the second input transistor is configured to receive a previous-stage scan signal, and the second terminal of the first input transistor and the second terminal of the second input transistor are coupled to the control terminal of the driving transistor; a pull-down circuit, coupled to the driving transistor and configured to pull down the current-stage scan control signal and the current-stage scan signal; and a capacitor, coupled to the driving transistor and configured to maintain the current-stage scan control signal, where in a first scan mode, the first terminal of the first input transistor receives the first clock signal, and the first terminal of the second input transistor receives a first scan direction control signal; and in a second scan mode, the first terminal of the first input transistor receives a second scan direction control signal, and the first terminal of the second input transistor receives the first clock signal.

公开(公告)号：US20170102801A1

公开(公告)日：2017-04-13

申请号：US15256871

申请日：2016-09-06

Applicant: AU Optronics Corporation

Inventor： Chien-Chuan KO ,  Meng-Chieh TSAI

IPC: G06F3/044

CPC classification number: G06F3/044 ,  G06F3/0416 ,  G09G3/20 ,  G09G3/3677 ,  G09G2310/0267 ,  G09G2310/0286

Abstract: A touch display apparatus is disclosed herein. The touch display apparatus has a timing controller outputting external signals; a touch driver for outputting touch driving signals according to the touch-enable signal; a scan driver having a multi-stage shift registers outputting scan signals, each shift register having a driving unit electrically connected to a driving node, outputting a first scan signal to an output end according to a clock signal; a pull-up unit outputting a driving voltage to the driving node according to a second scan signal; a pull-down control unit controlling a voltage level of the driving node according to the clock signal; a discharging unit adjusting the voltage level of the driving node according to a first control signal and the first scan signal, wherein the clock signal and the first control signal are in-phase periodic signals and respectively have a rising edge and a falling edge, the falling edge of the first control signal is ahead of that of the clock signal; and a pull-down unit electrically connected to the output end adjusting the voltage level of the output end, wherein the first control signal and the second control signal are complementary periodic signals.