公开(公告)号：US11430532B2

公开(公告)日：2022-08-30

申请号：US17094849

申请日：2020-11-11

Applicant: AU Optronics Corporation

Inventor： Yu-Jen Chen ,  Meng-Chieh Tsai

IPC: G11C19/28 ,  G09G3/3266 ,  G09G3/36 ,  G09G3/20

Abstract: A gate driving circuit includes a plurality of shift registers coupled in series. An nth shift register includes a driving circuit and a pull-down circuit. The driving circuit is electrically coupled to an output node and a first node. The driving circuit is configured to receive a first clock signal and output a gate signal according to the first clock signal. The pull-down circuit is electrically coupled to the output node. The pull-down circuit is configured to receive an (n−m)th gate signal and an (n+m)th gate signal, and pull-down the gate signal to a low voltage level according to one of the (n−m)th gate signal and the (n+m)th gate signal, wherein m and n are positive integers.

公开(公告)号：US11158225B2

公开(公告)日：2021-10-26

申请号：US16684664

申请日：2019-11-15

Applicant: AU OPTRONICS CORPORATION

Inventor： Wei-Chien Liao ,  Yu-Jen Chen ,  Meng-Chieh Tsai

IPC: G09G3/20 ,  H01L27/12

Abstract: A display device includes a plurality of pixel electrodes arranged in an array. A first switch electrically connected to a first pixel electrode of the pixel electrodes. A second switch electrically connected to a second pixel electrode of the pixel electrodes. The second switch is electrically connected between the first switch and a data line, and the first pixel electrode and the first pixel electrode are respectively located at two row of the pixel electrodes that are not adjacent to each other.