公开(公告)号：US20200111442A1

公开(公告)日：2020-04-09

申请号：US16200539

申请日：2018-11-26

Applicant: Au Optronics Corporation

Inventor： Wei-Chien Liao ,  Meng-Chieh Tsai

IPC: G09G5/00

Abstract: A display apparatus including a display panel and a plurality of common voltage generators is provided. The display panel has a plurality of pixel regions. The plurality of common voltage generators are coupled to the plurality of pixel regions respectively and generate a plurality of common voltages, wherein each of the plurality of common voltage generators respectively maintains each of the plurality of common voltages at a first voltage, a second voltage, and a third voltage in a plurality of first timing periods in a first polarity period and respectively maintains each of the plurality of common voltages at a fifth voltage, a fourth voltage, and the third voltage in a plurality of second timing periods in a second polarity period in a narrow view mode, wherein the first voltage>the second voltage>the third voltage>the fourth voltage>the fifth voltage.

公开(公告)号：US09922591B2

公开(公告)日：2018-03-20

申请号：US15357331

申请日：2016-11-21

Applicant: AU Optronics Corporation

Inventor： Chien-Chuan Ko ,  Chun-Hung Kuo ,  Meng-Chieh Tsai

IPC: G09G3/20 ,  G11C19/28 ,  G06F3/041 ,  G06F3/044

CPC classification number: G09G3/2092 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/044 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2354/00 ,  G11C19/28

Abstract: A display driving method includes: performing a display scan function and a display stop function during a plurality of frame periods; during one frame period, outputting, alternately and sequentially along a scan direction, N scan signals according to K clock signals when performing the display scan function, wherein each of the scan signals has an enable period of a scan line, the clock signals sequentially have a delay, and each of the clock signals is a periodic signal with K delays as one period; providing a driving control signal and disabling the clock signals when performing the display stop function during a display stop period, wherein an initiation time position of the display stop period is changed based on an offset between two neighboring frame periods, and the neighboring frame periods have no overlapping or interlacing interval.

公开(公告)号：US08653526B1

公开(公告)日：2014-02-18

申请号：US13832743

申请日：2013-03-15

Applicant: AU Optronics Corporation

Inventor： Chen-Yuan Lei ,  Meng-Chieh Tsai

IPC: H01L29/04 ,  H01L29/10 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20 ,  H01L29/15

CPC classification number: H01L27/1255 ,  G02F1/136213 ,  G02F1/1368

Abstract: A display panel having a display area and a gate driving area includes a gate line and plural pixel units in the display area, and a gate driver circuit in the gate driving area. The gate line connects to the pixel units. The gate driver circuit connects to the gate line. The gate driver includes a driving transistor and a driving storage capacitor stacked to each other to form a stack structure, which includes a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, a first semiconductor layer, a drain electrode, and a source electrode, which is connected to the gate line. The driving storage capacitor is formed by the first electrode, the first dielectric layer, and the second electrode. The driving transistor is formed by the second electrode, the second dielectric layer, the first semiconductor layer, the source electrode, and the drain electrode.

Abstract translation: 具有显示区域和栅极驱动区域的显示面板包括显示区域中的栅极线和多个像素单元，以及栅极驱动区域中的栅极驱动电路。 栅极线连接到像素单元。 栅极驱动电路连接到栅极线。 栅极驱动器包括彼此堆叠以形成堆叠结构的驱动晶体管和驱动存储电容器，其包括第一电极，第一电介质层，第二电极，第二电介质层，第一半导体层，漏电极 以及与栅极线连接的源电极。 驱动存储电容器由第一电极，第一电介质层和第二电极形成。 驱动晶体管由第二电极，第二电介质层，第一半导体层，源电极和漏极形成。

公开(公告)号：US11501697B2

公开(公告)日：2022-11-15

申请号：US17325161

申请日：2021-05-19

Applicant: Au Optronics Corporation

Inventor： Wei-Chien Liao ,  Meng-Chieh Tsai

IPC: G09G3/32

Abstract: A pixel circuit and a display device are provided. The pixel circuit is utilized for driving a light emitting diode. The pixel circuit includes a storage capacitor, a selector, a memory device, and a write switch. The storage capacitor is coupled to the light emitting diode. The selector selects a first signal or a second signal to the storage capacitor according to a stored data. The memory device is coupled to the selector. The memory device stores a written data to obtain the stored data. The write switch is coupled to the memory device. The write switch writes in the written data to the memory device while the pixel circuit is in transition of operation modes.

公开(公告)号：US20200005696A1

公开(公告)日：2020-01-02

申请号：US16218494

申请日：2018-12-13

Applicant: Au Optronics Corporation

Inventor： Wei-Chien Liao ,  Meng-Chieh Tsai

IPC: G09G3/20 ,  H01L27/12

Abstract: A display device includes a plurality of scan lines, a plurality of data lines, a plurality of pixel units, a plurality of gate driving circuits, and a plurality of connection lines. The scan lines extend in a first direction. The data lines extend in a second direction. The gate driving circuits extend in the first direction, and each of the gate driving circuits crosses through at least two of the pixel units. At least two gate driving circuits are included between two adjacent rows of the pixel units. The connection lines extend in the second direction and are electrically connected to the gate driving circuits. At least part of the connection lines overlap the data lines. The connection lines include a plurality of output lines and a plurality of signal lines. The output lines are electrically connected to the scan lines.

公开(公告)号：US20130135719A1

公开(公告)日：2013-05-30

申请号：US13677307

申请日：2012-11-15

Applicant: Au Optronics Corporation

Inventor： Meng-Chieh Tsai

IPC: G02B27/22

CPC classification number: G02B27/2214 ,  H04N13/31 ,  H04N13/317

Abstract: A stereo display device includes a display panel and a parallax barrier panel. The display panel includes a pixel array having pixel units, each of which includes sub-pixels. The parallax barrier panel at one side of the display panel includes a first substrate, first electrodes, second electrodes, a second substrate, third electrodes, fourth electrodes, and a birefringence medium. The first and second electrodes are arranged on the first substrate alternately; an extension direction of the first and second electrodes is parallel to the X-direction. The third and fourth electrodes are arranged on the second substrate alternately; an extension direction of the third and fourth electrodes is not parallel to the X-direction; an included angle between the extension direction of the third and fourth electrodes and the Y-direction is substantially greater than 0° and smaller than 45°. The birefringence medium is disposed between the first and second substrates.

Abstract translation: 立体显示装置包括显示面板和视差屏障面板。 显示面板包括具有像素单元的像素阵列，每个像素单元包括子像素。 显示面板一侧的视差屏障面板包括第一基板，第一电极，第二电极，第二基板，第三电极，第四电极和双折射介质。 第一和第二电极交替地布置在第一基板上; 第一和第二电极的延伸方向平行于X方向。 第三和第四电极交替地布置在第二基板上; 第三和第四电极的延伸方向不平行于X方向; 第三和第四电极的延伸方向和Y方向之间的夹角大致大于0°且小于45°。 双折射介质设置在第一和第二基底之间。

公开(公告)号：US09921702B2

公开(公告)日：2018-03-20

申请号：US15256871

申请日：2016-09-06

Applicant: AU Optronics Corporation

Inventor： Chien-Chuan Ko ,  Meng-Chieh Tsai

IPC: G06F3/044 ,  G06F3/041 ,  G09G3/36 ,  G09G3/20

CPC classification number: G06F3/044 ,  G06F3/0416 ,  G09G3/20 ,  G09G3/3677 ,  G09G2310/0267 ,  G09G2310/0286

Abstract: A touch display apparatus is disclosed herein. The touch display apparatus has a timing controller outputting external signals; a touch driver for outputting touch driving signals according to the touch-enable signal; a scan driver having a multi-stage shift registers outputting scan signals, each shift register having a driving unit electrically connected to a driving node, outputting a first scan signal to an output end according to a clock signal; a pull-up unit outputting a driving voltage to the driving node according to a second scan signal; a pull-down control unit controlling a voltage level of the driving node according to the clock signal; a discharging unit adjusting the voltage level of the driving node according to a first control signal and the first scan signal, wherein the clock signal and the first control signal are in-phase periodic signals and respectively have a rising edge and a falling edge, the falling edge of the first control signal is ahead of that of the clock signal; and a pull-down unit electrically connected to the output end adjusting the voltage level of the output end, wherein the first control signal and the second control signal are complementary periodic signals.

公开(公告)号：US20170123556A1

公开(公告)日：2017-05-04

申请号：US15189468

申请日：2016-06-22

Applicant: AU Optronics Corporation

Inventor： Chih-Lung LIN ,  Po-Chun Lai ,  Chia-En Wu ,  Chien-Chuan Ko ,  Meng-Chieh Tsai

IPC: G06F3/041 ,  G09G3/36 ,  G11C19/28 ,  G06F3/044

CPC classification number: G06F3/0416 ,  G06F3/0412 ,  G06F3/044 ,  G09G3/20 ,  G09G3/3677 ,  G09G3/3696 ,  G09G2300/0842 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/28

Abstract: A shift register circuit includes a driving unit outputting a first scan signal according to a first clock signal; a pull up unit outputting a driving voltage according to one of a second scan signal and a third scan signal; a pull down unit pulling down voltage of an output end according to a second clock signal; a pull down control unit controlling the voltage of the output end and a driving node according to the first clock signal; a reset unit pulling down the voltage level of the driving node according to a touch-enable signal; and an electric storage unit adjusting the voltage of the driving node according to a touch-stop signal. When the touch-enable signal is enabled, the clock signals and the touch-stop signal are disabled, and when the touch-stop signal is enabled, the clock signals and the touch-enable signal are disabled.

公开(公告)号：US11430532B2

公开(公告)日：2022-08-30

申请号：US17094849

申请日：2020-11-11

Applicant: AU Optronics Corporation

Inventor： Yu-Jen Chen ,  Meng-Chieh Tsai

IPC: G11C19/28 ,  G09G3/3266 ,  G09G3/36 ,  G09G3/20

Abstract: A gate driving circuit includes a plurality of shift registers coupled in series. An nth shift register includes a driving circuit and a pull-down circuit. The driving circuit is electrically coupled to an output node and a first node. The driving circuit is configured to receive a first clock signal and output a gate signal according to the first clock signal. The pull-down circuit is electrically coupled to the output node. The pull-down circuit is configured to receive an (n−m)th gate signal and an (n+m)th gate signal, and pull-down the gate signal to a low voltage level according to one of the (n−m)th gate signal and the (n+m)th gate signal, wherein m and n are positive integers.

公开(公告)号：US20220114950A1

公开(公告)日：2022-04-14

申请号：US17325161

申请日：2021-05-19

Applicant: Au Optronics Corporation

Inventor： Wei-Chien Liao ,  Meng-Chieh Tsai

IPC: G09G3/32

Abstract: A pixel circuit and a display device are provided. The pixel circuit is utilized for driving a light emitting diode. The pixel circuit includes a storage capacitor, a selector, a memory device, and a write switch. The storage capacitor is coupled to the light emitting diode. The selector selects a first signal or a second signal to the storage capacitor according to a stored data. The memory device is coupled to the selector. The memory device stores a written data to obtain the stored data. The write switch is coupled to the memory device. The write switch writes in the written data to the memory device while the pixel circuit is in transition of operation modes.