公开(公告)号：US06665846B2

公开(公告)日：2003-12-16

申请号：US09905855

申请日：2001-07-13

申请人： Achim Rein ,  Martin Frerichs

发明人： Achim Rein ,  Martin Frerichs

IPC分类号： G06F1750

CPC分类号： G06F17/5081

摘要： With the assistance of a computer, in order to verify a layout of an integrated circuit, for one or more selected interconnection networks that are contained in the layout, the capacitance with respect to other interconnection networks contained in the layout is calculated as follows: A filter polygon is determined, which corresponds to the form of the selected interconnection network, the dimensions of the filter polygon are enlarged by a predeterminable extent relative to the dimensions of the selected interconnection networks. The portions of the other interconnection networks which overlap the filter polygon are determined, and the capacitance between the selected interconnection networks and the portions of the other interconnection networks which overlap the filter polygon is determined. In order to process large volumes of data, it is advantageous in this case to split the filter polygon into partitioning cells having a predetermined maximum dimension, for which the capacitance between the selected interconnection networks and the portions of the other interconnection networks which overlap the respective partitioning cell is then calculated.

公开(公告)号：US06865727B2

公开(公告)日：2005-03-08

申请号：US10114796

申请日：2002-04-02

申请人： Martin Frerichs ,  Achim Rein

发明人： Martin Frerichs ,  Achim Rein

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method for verifying a layout of an integrated circuit with the aid of a computer and the fabrication of the circuit applying the method includes the steps of inserting several floating structures, namely fill structures, in a layout wiring plane, configuring the structures into structural regions, taking the regions into consideration with respect to the wiring capacities in the vicinity of these structures for a low computational outlay, and, for each structural region (3), defining a boundary polynomial that is modeled according to the outer margins of the structural region. In the calculation of the capacity coefficient, a structural region can be taken into consideration as a whole by a large filler polygon.

摘要翻译： 借助于计算机来验证集成电路的布局的方法以及应用该方法的电路的制造包括以下步骤：在布局布线平面中插入若干浮动结构，即填充结构，将结构配置成结构区域 考虑到这些结构附近的布线容量的区域，对于低计算支出，并且对于每个结构区域（3），定义根据结构区域的外边缘建模的边界多项式 。 在容量系数的计算中，可以通过大填料多边形整体考虑结构区域。