公开(公告)号：US11023241B2

公开(公告)日：2021-06-01

申请号：US16106515

申请日：2018-08-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrej Kocev ,  Jay Fleischman ,  Kai Troester ,  Johnny C. Chu ,  Tim J. Wilkens ,  Neil Marketkar ,  Michael W. Long

IPC: G06F9/38 ,  G06F9/30

Abstract: Systems and methods selectively bypass address-generation hardware in processor instruction pipelines. In an embodiment, a processor includes an address-generation stage and an address-generation-bypass-determination unit (ABDU). The ABDU receives a load/store instruction. If an effective address for the load/store instruction is not known at the ABDU, the ABDU routes the load/store instruction via the address-generation stage of the processor. If, however, the effective address of the load/store instruction is known at the ABDU, the ABDU routes the load/store instruction to bypass the address-generation stage of the processor.