公开(公告)号：US11099846B2

公开(公告)日：2021-08-24

申请号：US16013069

申请日：2018-06-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Krishnan V. Ramani ,  Chetana N. Keltcher

IPC: G06F9/30 ,  G06F9/38

Abstract: A method and apparatus generates control information that indicates whether to change a counter value associated with a particular load instruction. In response to the control information, the method and apparatus causes a hysteresis effect for operating between a speculative mode and a non-speculative mode based on the counter value. The hysteresis effect is in favor of the non-speculative mode. The method and apparatus causes the hysteresis effect by incrementing the counter value associated with the particular load instruction by a first value or decrementing the counter value by a second value. The first value is greater than the second value.

公开(公告)号：US20230305849A1

公开(公告)日：2023-09-28

申请号：US17704627

申请日：2022-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Chetana N. Keltcher ,  Alok Garg ,  Paul S. Keltcher

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3802 ,  G06F9/30043

Abstract: Array of pointers prefetching is described. In accordance with described techniques, a pointer target instruction is detected by identifying that a destination location of a load instruction is used in an address compute for a memory operation and the load instruction is included in a sequence of load instructions having addresses separated by a step size. An instruction for fetching data of a future load instruction is injected in an instruction stream of a processor. The data of the future load instruction is stored in a temporary register. An additional instruction is injected in the instruction stream for prefetching a pointer target based on an address of the memory operation and the data of the future load instruction.

公开(公告)号：US20230297381A1

公开(公告)日：2023-09-21

申请号：US17699855

申请日：2022-03-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Chetana N. Keltcher ,  Alok Garg ,  Paul S Keltcher

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30043

Abstract: Load dependent branch prediction is described. In accordance with described techniques, a load dependent branch instruction is detected by identifying that a destination location of a load instruction is used in an operation for determining whether a conditional branch is taken or not taken. The load instruction is included in a sequence of load instructions having addresses separated by a step size. An instruction is injected in an instruction stream of a processor for fetching data of a future load instruction using an address of the load instruction offset by a distance based on the step size. An additional instruction is injected in the instruction stream of the processor for precomputing an outcome of a load dependent branch using an address computed based on an address of the operation and the data of the future load instruction.

公开(公告)号：US20190391808A1

公开(公告)日：2019-12-26

申请号：US16013069

申请日：2018-06-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Krishnan V. Ramani ,  Chetana N. Keltcher

IPC: G06F9/30

Abstract: A method and apparatus generates control information that indicates whether to change a counter value associated with a particular load instruction. In response to the control information, the method and apparatus causes a hysteresis effect for operating between a speculative mode and a non-speculative mode based on the counter value. The hysteresis effect is in favor of the non-speculative mode. The method and apparatus causes the hysteresis effect by incrementing the counter value associated with the particular load instruction by a first value or decrementing the counter value by a second value. The first value is greater than the second value.