公开(公告)号：US20250103424A1

公开(公告)日：2025-03-27

申请号：US18653719

申请日：2024-05-02

Applicant: Advanced Micro Devices, Inc.

Inventor： David Da-Wei LIN ,  Edoardo PRETE ,  Tsun-Ho LIU

IPC: G06F11/10

Abstract: A memory system includes a memory controller and memory circuitry. The memory controller outputs a first training signal. The memory circuitry is coupled to the memory controller. The memory circuitry includes a memory device and multiplexing data buffer circuitry. The multiplexing data buffer circuitry is coupled to the memory device. The multiplexing data buffer circuitry includes first circuitry and second circuitry. The second circuitry is coupled to the memory device. The second circuitry receives the first training signal from memory controller comprising first training data associated with the first circuitry, writes the first training data to the memory device, and read the written first training data from the memory device, and outputs the written first training data to the memory controller. The memory controller is configured to determine equalization parameters for the first circuitry based on the written first training data.