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公开(公告)号:US20150199150A1
公开(公告)日:2015-07-16
申请号:US14156071
申请日:2014-01-15
Applicant: Advanced Micro Devices, Inc.
Inventor: Hye Ran Jeon , Gabriel H. Loh
IPC: G06F3/06
CPC classification number: G11C7/1006 , G06F3/061 , G06F3/0659 , G06F3/0688 , G11C7/1078 , G11C11/4093
Abstract: The described embodiments include a memory with a memory array and logic circuits. In these embodiments, logical operations are performed on data from the memory array by reading the data from the memory array, performing a logical operation on the data in the logic circuits, and writing the data back to the memory array. In these embodiments, the logic circuit is located in the memory so that the data read from the memory array need not be sent to another circuit (e.g., a processor coupled to the memory, etc.) to have the logical operation performed.
Abstract translation: 所描述的实施例包括具有存储器阵列和逻辑电路的存储器。 在这些实施例中,通过从存储器阵列读取数据,对逻辑电路中的数据执行逻辑运算,并将数据写回存储器阵列,对来自存储器阵列的数据执行逻辑运算。 在这些实施例中,逻辑电路位于存储器中,使得从存储器阵列读取的数据不需要发送到另一个电路(例如,耦合到存储器的处理器等)以执行逻辑操作。
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公开(公告)号:US09361956B2
公开(公告)日:2016-06-07
申请号:US14156071
申请日:2014-01-15
Applicant: Advanced Micro Devices, Inc.
Inventor: Hye Ran Jeon , Gabriel H. Loh
CPC classification number: G11C7/1006 , G06F3/061 , G06F3/0659 , G06F3/0688 , G11C7/1078 , G11C11/4093
Abstract: The described embodiments include a memory with a memory array and logic circuits. In these embodiments, logical operations are performed on data from the memory array by reading the data from the memory array, performing a logical operation on the data in the logic circuits, and writing the data back to the memory array. In these embodiments, the logic circuit is located in the memory so that the data read from the memory array need not be sent to another circuit (e.g., a processor coupled to the memory, etc.) to have the logical operation performed.
Abstract translation: 所描述的实施例包括具有存储器阵列和逻辑电路的存储器。 在这些实施例中,通过从存储器阵列读取数据,对逻辑电路中的数据执行逻辑运算,并将数据写回存储器阵列,对来自存储器阵列的数据执行逻辑运算。 在这些实施例中,逻辑电路位于存储器中,使得从存储器阵列读取的数据不需要发送到另一个电路(例如,耦合到存储器的处理器等)以执行逻辑操作。
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