公开(公告)号：US20240304241A1

公开(公告)日：2024-09-12

申请号：US18181054

申请日：2023-03-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Richard T. Schultz ,  Kerrie Vercant Underhill

IPC: G11C11/419 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H10B10/00

CPC classification number: G11C11/419 ,  H01L23/5283 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/78696 ,  H10B10/125

Abstract: An apparatus and method for efficiently creating layout for memory bit cells are described. In various implementations, a memory bit cell uses pairs of transistors that are vertically stacked gate all around (GAA) transistors with gate terminals forming a T-shape with respect to one another and a single gate contact that overlaps only one active layer of the two active layers of the pair. Transistors of such a pair of field effect transistors (FETs) are referred to as TFETs. With respect to one another, the active layers of TFETs use opposite doping polarities and conduct current in an orthogonal direction. A non-overlapping distance between top and bottom active layers of a pair of TFETs is at least a width of a drain/source contact. The orthogonal current flow of the top and bottom active layers simplifies local connections that reduces the resistance and capacitance of the signal routes.