公开(公告)号：US20250110861A1

公开(公告)日：2025-04-03

申请号：US18374815

申请日：2023-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Moumita Dey ,  Varun Agrawal

IPC: G06F12/02

Abstract: In accordance with the described techniques for data compression using reconfigurable hardware based on data redundancy patterns, a computing device includes a memory, processing-in-memory units, a host processing unit, and a compression unit having reconfigurable logic for performing multiple compression algorithms. The host processing unit issues processing-in-memory requests instructing the processing-in-memory units to scan a block of the memory for one or more data redundancy patterns, and to identify a compression algorithm of the multiple compression algorithms based on the one or more data redundancy patterns. Further, the host processing unit issues a memory request to access a memory address in the block of the memory. The memory request causes data of the memory address to be communicated from the block of the memory to the compression unit to be compressed using the compression algorithm.