公开(公告)号：US10067718B2

公开(公告)日：2018-09-04

申请号：US15274178

申请日：2016-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Glennis Eliagh Covington ,  Kevin M. Brandl ,  Nienchi Hu ,  Shannon T. Kesner

IPC: G06F12/00 ,  G06F3/06

Abstract: Dynamic random access memory (DRAM) chips in memory modules include multi-purpose registers (MPRs) having pre-defined data patterns which, when selected, are accessed with read commands and output on data lines for performing read training. The MPRs are accessed by issuing read commands to specific register addresses to request reads from specific MPR locations. In some embodiments, read training for memory modules includes addressing, for a first half of a memory module, a read command to a first register address and performing read training using a first set of bit values received in response to addressing using the first register address. For a second half of the memory module, the same read command is used, but read training is performed using a second set of bit values received in response to addressing using the first register address.

公开(公告)号：US20180088862A1

公开(公告)日：2018-03-29

申请号：US15274178

申请日：2016-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Glennis Eliagh Covington ,  Kevin M. Brandl ,  Nienchi Hu ,  Shannon T. Kesner

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0683 ,  G11C5/04 ,  G11C7/00 ,  G11C29/026 ,  G11C29/028

Abstract: Dynamic random access memory (DRAM) chips in memory modules include multi-purpose registers (MPRs) having pre-defined data patterns which, when selected, are accessed with read commands and output on data lines for performing read training. The MPRs are accessed by issuing read commands to specific register addresses to request reads from specific MPR locations. In some embodiments, read training for memory modules includes addressing, for a first half of a memory module, a read command to a first register address and performing read training using a first set of bit values received in response to addressing using the first register address. For a second half of the memory module, the same read command is used, but read training is performed using a second set of bit values received in response to addressing using the first register address.