公开(公告)号：US20190067036A1

公开(公告)日：2019-02-28

申请号：US15685864

申请日：2017-08-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung YEN ,  Kuang-Hsiung CHEN ,  Shing-Cheng LIANG ,  Pei-Yu HSU

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/482

Abstract: A semiconductor package includes a die and a patterned conductive layer electrically connected to the die. The patterned conductive layer includes a connection pad and a trace. The semiconductor package further includes an encapsulation layer encapsulating the die and the patterned conductive layer. The semiconductor package further includes an electrical connection element disposed on the connection pad and a protection layer including a sidewall portion surrounding the electrical connection element.