公开(公告)号：US20210028150A1

公开(公告)日：2021-01-28

申请号：US16523787

申请日：2019-07-26

申请人： Advanced Semiconductor Engineering, Inc.

发明人： You-Lung YEN ,  Bernd Karl APPELT ,  Kay Stefan ESSIG

IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

摘要： A semiconductor device package includes a substrate, a stacked structure and an encapsulation layer. The substrate includes a circuit layer, a first surface and a second surface opposite to the first surface. The substrate defines at least one cavity through the substrate. The stacked structure includes a first semiconductor die disposed on the first surface and electrically connected on the circuit layer, and at least one second semiconductor die stacked on the first semiconductor die and electrically connected to the first semiconductor die. The second semiconductor die is at least partially inserted into the cavity. The encapsulation layer is disposed in the cavity and at least entirely encapsulating the second semiconductor die.

公开(公告)号：US20200350180A1

公开(公告)日：2020-11-05

申请号：US16403393

申请日：2019-05-03

申请人： Advanced Semiconductor Engineering, Inc.

发明人： You-Lung YEN ,  Bernd Karl APPELT ,  Kay Stefan ESSIG

IPC分类号： H01L21/48 ,  H01L23/495 ,  H01L23/552 ,  H01L21/56 ,  H01Q1/22 ,  H01Q1/52

摘要： At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a carrier having a first surface and a second surface opposite to the first surface, an encapsulant, and an antenna. The encapsulant is disposed on the first surface of the carrier. The antenna is disposed on the encapsulant. The antenna includes a seed layer and a conductive layer.

公开(公告)号：US20190067036A1

公开(公告)日：2019-02-28

申请号：US15685864

申请日：2017-08-24

申请人： Advanced Semiconductor Engineering, Inc.

发明人： You-Lung YEN ,  Kuang-Hsiung CHEN ,  Shing-Cheng LIANG ,  Pei-Yu HSU

IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/482

摘要： A semiconductor package includes a die and a patterned conductive layer electrically connected to the die. The patterned conductive layer includes a connection pad and a trace. The semiconductor package further includes an encapsulation layer encapsulating the die and the patterned conductive layer. The semiconductor package further includes an electrical connection element disposed on the connection pad and a protection layer including a sidewall portion surrounding the electrical connection element.

公开(公告)号：US20150348931A1

公开(公告)日：2015-12-03

申请号：US14700060

申请日：2015-04-29

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chih-Cheng LEE ,  Yuan Chang SU ,  Cheng-Lin HO ,  Chung-Ming WU ,  You-Lung YEN

IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76801 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/11334 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81801 ,  H01L2924/014 ,  H01L2924/00014

摘要： The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer. The substrate includes a first patterned metal layer, a second patterned metal layer spaced from the first patterned metal layer, and a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer. The dielectric layer covers the second patterned metal layer. The dielectric layer defines first openings exposing the second patterned metal layer, and further defines a via opening extending from the first patterned metal layer to the second patterned metal layer. A conductive material is disposed in the via and electrically connects the first patterned metal layer to the second patterned metal layer. The carrier layer defines second openings exposing the second patterned metal layer.

摘要翻译： 本公开涉及半导体衬底，半导体封装结构及其制造方法。 一种方法包括提供衬底和载体层。 衬底包括第一图案化金属层，与第一图案化金属层间隔开的第二图案化金属层，以及设置在第一图案化金属层和第二图案化金属层之间的介电层。 电介质层覆盖第二图案化金属层。 电介质层限定暴露第二图案化金属层的第一开口，并且还限定从第一图案化金属层延伸到第二图案化金属层的通孔。 导电材料设置在通孔中并将第一图案化金属层电连接到第二图案化金属层。 载体层限定暴露第二图案化金属层的第二开口。

公开(公告)号：US20230042800A1

公开(公告)日：2023-02-09

申请号：US17396604

申请日：2021-08-06

申请人： Advanced Semiconductor Engineering, Inc.

发明人： You-Lung YEN ,  Bernd Karl APPELT

IPC分类号： H01L23/433 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

摘要： An electronic package is provided in the present disclosure. The electronic package comprises: a heat spreading component; a first electronic component disposed on the heat spreading component; and a second electronic component disposed on the first electronic component, wherein the second electronic component comprises an interconnection structure passing through the second electronic component and electrically connecting the first electronic component. In this way, through the use of the interconnection structure, the heat dissipation of the electronic components in the package can be improved. Also, through the use of the encapsulant, the stacked electronic components can be protected by the encapsulant so as to avoid being damaged.

公开(公告)号：US20220367384A1

公开(公告)日：2022-11-17

申请号：US17321139

申请日：2021-05-14

申请人： Advanced Semiconductor Engineering, Inc.

发明人： You-Lung YEN ,  Bernd Karl APPELT ,  Kay Stefan ESSIG

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L23/433

摘要： A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate, a semiconductor device, an encapsulant, a balance structure, and a warpage-resistant layer. The semiconductor device is disposed on the substrate. The encapsulant encapsulates the semiconductor device. The balance structure is on the semiconductor device and contacting the encapsulant. The warpage-resistant layer is between the semiconductor device and the balance structure. The encapsulant contacts a lateral surface of the warpage-resistant layer.

公开(公告)号：US20220336332A1

公开(公告)日：2022-10-20

申请号：US17233294

申请日：2021-04-16

申请人： Advanced Semiconductor Engineering, Inc.

发明人： You-Lung YEN ,  Bernd Karl APPELT

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L23/053 ,  H01L21/48 ,  H01L21/56

摘要： A conductive structure, a package structure and a method for manufacturing the same are provided. The conductive structure includes a main portion, a first electrical contact, a second electrical contact, a first post and a second post. The main portion has a first surface and a second surface opposite to the first surface. The first electrical contact is disposed adjacent to the first surface of the main portion. The second electrical contact is disposed adjacent to the second surface of the main portion and electrically connected to the first electrical contact. The first post is electrically connected to the first electrical contact. The second post is electrically connected to the second electrical contact.

公开(公告)号：US20220115288A1

公开(公告)日：2022-04-14

申请号：US17066407

申请日：2020-10-08

申请人： Advanced Semiconductor Engineering, Inc.

发明人： You-Lung YEN ,  Bernd Karl APPELT ,  Kay Stefan ESSIG

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L21/56

摘要： A substrate structure, a semiconductor package structure including the same and a method for manufacturing the same are provided. The substrate structure includes a first passivation layer, a first circuit layer and a first protection layer. The first passivation layer has a first surface and a second surface opposite to the first surface. The first circuit layer has an outer lateral surface. A first portion of the first circuit layer is disposed in the first passivation layer. The first protection layer is disposed on a second portion of the first circuit layer and exposed from the first surface of the first passivation layer. The outer lateral surface of the first circuit layer is covered by the first passivation layer or the first protection layer.

公开(公告)号：US20210118775A1

公开(公告)日：2021-04-22

申请号：US16655178

申请日：2019-10-16

申请人： Advanced Semiconductor Engineering, Inc.

发明人： You-Lung YEN ,  Bernd Karl APPELT

IPC分类号： H01L23/495 ,  H01L23/00

摘要： A leadframe includes a first conductive layer, a plurality of conductive pillars and a first package body. The first conductive layer has a first surface and a second surface opposite to the first surface. The plurality of conductive pillars are disposed on the first surface of the first conductive layer. The first package body is disposed on the first surface of the first conductive layer and covers the conductive pillars. The conductive pillars and the first conductive layer are integratedly formed.

公开(公告)号：US20230037201A1

公开(公告)日：2023-02-02

申请号：US17390697

申请日：2021-07-30

申请人： Advanced Semiconductor Engineering, Inc.

发明人： You-Lung YEN ,  Bernd Karl Appelt

IPC分类号： H01L23/367 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065

摘要： A electronic package and a method of manufacturing the same are provided. The electronic package includes an electronic component, a thermal spreading element, and an encapsulant. The electronic component has a first surface. The thermal spreading element is disposed over the electronic component and has a first surface facing the first surface of the electronic component. The encapsulant covers the electronic component and has a first surface closer to the first surface of the thermal spreading element than the first surface of the electronic component.