公开(公告)号：US20200228105A1

公开(公告)日：2020-07-16

申请号：US16648192

申请日：2018-10-01

Applicant: Agency for Science, Technology and Research

Inventor： Jun Zhou ,  Xin Liu ,  Jingjing Lan

IPC: H03K5/1252 ,  H03K5/24

Abstract: Various embodiments may relate to a clocking circuit arrangement. The clocking circuit arrangement may include a clock source, as well as a global monitoring circuit arrangement including a monitoring tunable clock buffer, a reference clock buffer, a glitch capturing circuit arrangement, and a voltage generation circuit arrangement. The clocking circuit arrangement may further include a main circuit arrangement including one or more further tunable clock buffers.