公开(公告)号：US09746877B2

公开(公告)日：2017-08-29

申请号：US14897134

申请日：2014-06-05

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

Inventor： Jun Zhou ,  Xin Liu

IPC: H03K3/13 ,  G06F1/08 ,  H03K3/037

CPC classification number: G06F1/08 ,  H03K3/0375

Abstract: A method for detecting and correcting an error in a circuit is provided. The circuit is configured to receive an input signal and clock the input signal with a rising and falling timing signal. The method includes detecting late arrival signal transition of the input signal, at an intermediate point of a path, the path being one through which the input signal transits. The method further includes predicting an error in the input signal in response to detecting the late arrival signal transition at the intermediate point of the path. In addition, the method includes correcting the error in the input signal by manipulating the timing signal and/or a supply voltage.

公开(公告)号：US09425905B2

公开(公告)日：2016-08-23

申请号：US14022122

申请日：2013-09-09

Applicant: Agency for Science, Technology and Research

Inventor： Jung Hyup Lee ,  Vishal Vinayak Kulkarni ,  Tao Wang ,  Jun Zhou ,  Xin Liu ,  Minkyu Je

IPC: H04B1/02 ,  H04B13/00

CPC classification number: H04B13/005

Abstract: In various embodiments of the present disclosure, there is provided a receiver for body channel communication. The receiver includes an electrode configured to receive an incoming signal transmitted as a multi-level transmission signal from a transmitter through a body channel, a differentiator configured to obtain a time derivative of the incoming signal indicating a plurality of data transitions, and an analog to digital converter configured to generate a multi-level output signal representing the multi-level transmission signal based on the plurality of data transitions. A corresponding method of controlling a receiver for body channel communications is provided.

Abstract translation: 在本公开的各种实施例中，提供了一种用于身体信道通信的接收机。 接收机包括被配置为接收通过身体信道从发射机作为多级传输信号发送的输入信号的电极，被配置为获得指示多个数据转换的输入信号的时间导数的微分器，以及模拟到 数字转换器，被配置为基于所述多个数据转换来生成表示所述多级传输信号的多电平输出信号。 提供了一种用于控制身体信道通信的接收机的相应方法。

公开(公告)号：US09362916B2

公开(公告)日：2016-06-07

申请号：US14706627

申请日：2015-05-07

Applicant: Agency for Science, Technology and Research

Inventor： Jun Zhou

IPC: H03K19/0175

CPC classification number: H03K19/017509

Abstract: In various embodiments, a circuit arrangement may be provided. The circuit arrangement may include a level shifting stage configured to be coupled to a first reference voltage, the level shifting stage having an output node. The circuit arrangement may further include a first input electrode in electrical connection with the level shifting stage. The circuit arrangement may also include a second input electrode in electrical connection with the level shifting stage. The circuit arrangement may further include a load having a first end and a second end, the first end coupled to the level shifting stage and the second end for coupling to a second reference voltage. In addition, the circuit arrangement may include a bypass circuit element connected in parallel to the load. The bypass circuit element may be configured to allow current to flow through upon application of an external voltage for bypassing the load.

公开(公告)号：US09374090B2

公开(公告)日：2016-06-21

申请号：US14895758

申请日：2014-06-04

Applicant: Agency for Science, Technology and Research

Inventor： Jun Zhou ,  Chao Wang

IPC: H03K19/00 ,  H03K19/0175

CPC classification number: H03K19/0013 ,  H03K3/356165 ,  H03K3/356182 ,  H03K19/017509

Abstract: A circuit arrangement may be provided including a level shifting stage configured to be coupled to a first reference voltage and a second reference voltage. The circuit arrangement may also include a first input electrode in electrical connection with the level shifting stage for coupling a first input voltage and a second input electrode in electrical connection with the level shifting stage for coupling a second input voltage. The level shifting stage may be configured to generate an output voltage above a predetermined output level at the output node due to the first reference voltage when the first input voltage is in the first logic state and the second input voltage is in the second logic state. The circuit arrangement may also include a feedback circuit coupled to the output stage and the level shifting stage and a voltage stabilization circuit coupled to the level shifting stage.

Abstract translation: 可以提供电路装置，其包括电平移位级，配置为耦合到第一参考电压和第二参考电压。 电路装置还可以包括与电平移位级电连接的用于耦合第一输入电压的第一输入电极和与电平移位级电连接的用于耦合第二输入电压的第二输入电极。 电平移位级可以被配置为当第一输入电压处于第一逻辑状态并且第二输入电压处于第二逻辑状态时，由于第一参考电压而在输出节点处产生高于预定输出电平的输出电压。 电路装置还可以包括耦合到输出级和电平移位级的反馈电路以及耦合到电平转换级的稳压电路。

公开(公告)号：US20160118985A1

公开(公告)日：2016-04-28

申请号：US14895758

申请日：2014-06-04

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

Inventor： Jun Zhou ,  Chao Wang

IPC: H03K19/00 ,  H03K19/0175

CPC classification number: H03K19/0013 ,  H03K3/356165 ,  H03K3/356182 ,  H03K19/017509

Abstract: A circuit arrangement may be provided including a level shifting stage configured to be coupled to a first reference voltage and a second reference voltage. The circuit arrangement may also include a first input electrode in electrical connection with the level shifting stage for coupling a first input voltage and a second input electrode in electrical connection with the level shifting stage for coupling a second input voltage. The level shifting stage may be configured to generate an output voltage above a predetermined output level at the output node due to the first reference voltage when the first input voltage is in the first logic state and the second input voltage is in the second logic state. The circuit arrangement may also include a feedback circuit coupled to the output stage and the level shifting stage and a voltage stabilization circuit coupled to the level shifting stage.

Abstract translation: 可以提供电路装置，其包括电平移位级，配置为耦合到第一参考电压和第二参考电压。 电路装置还可以包括与电平移位级电连接的用于耦合第一输入电压的第一输入电极和与电平移位级电连接的用于耦合第二输入电压的第二输入电极。 电平移位级可以被配置为当第一输入电压处于第一逻辑状态并且第二输入电压处于第二逻辑状态时，由于第一参考电压，在输出节点处产生高于预定输出电平的输出电压。 电路装置还可以包括耦合到输出级和电平移位级的反馈电路以及耦合到电平转换级的稳压电路。

公开(公告)号：US09717430B2

公开(公告)日：2017-08-01

申请号：US14897581

申请日：2014-06-12

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

Inventor： Xin Liu ,  Jun Zhou

IPC: H03M1/00 ,  A61B5/04 ,  A61B5/00 ,  A61B5/0428 ,  A61B5/0472 ,  A61B5/0476 ,  G01R19/25

CPC classification number: A61B5/04012 ,  A61B5/0428 ,  A61B5/0472 ,  A61B5/0476 ,  A61B5/4812 ,  A61B5/4836 ,  A61B5/7203 ,  G01R19/2509

Abstract: An electrocardiogram (ECG) signal processing system is provided. The ECG signal processing system comprises an analog-to-digital converter (ADC) configured to convert an input analog ECG signal into a digital ECG signal, and a digital signal processing engine (DSPE) coupled to the ADC to receive the digital ECG signal. The DSPE is configured to decompose and reconstruct the digital ECG signal. A dynamic system clock source is coupled to the ADC and the DSPE for dynamic signal sampling, the dynamic system clock source clocking the ADC and the DSPE at a first frequency f1 to detect one or more first parameters of the input analog ECG signal and at a second frequency f2 to detect one or more second parameters of the input analog ECG signal.

公开(公告)号：US20200228105A1

公开(公告)日：2020-07-16

申请号：US16648192

申请日：2018-10-01

Applicant: Agency for Science, Technology and Research

Inventor： Jun Zhou ,  Xin Liu ,  Jingjing Lan

IPC: H03K5/1252 ,  H03K5/24

Abstract: Various embodiments may relate to a clocking circuit arrangement. The clocking circuit arrangement may include a clock source, as well as a global monitoring circuit arrangement including a monitoring tunable clock buffer, a reference clock buffer, a glitch capturing circuit arrangement, and a voltage generation circuit arrangement. The clocking circuit arrangement may further include a main circuit arrangement including one or more further tunable clock buffers.

公开(公告)号：US09054694B2

公开(公告)日：2015-06-09

申请号：US13905468

申请日：2013-05-30

Applicant: Agency for Science, Technology and Research

Inventor： Jun Zhou

IPC: H03K19/0175

CPC classification number: H03K19/017509

Abstract: In various embodiments, a circuit arrangement may be provided. The circuit arrangement may include a level shifting stage configured to be coupled to a first reference voltage, the level shifting stage having an output node. The circuit arrangement may further include a first input electrode in electrical connection with the level shifting stage. The circuit arrangement may also include a second input electrode in electrical connection with the level shifting stage. The circuit arrangement may further include a load having a first end and a second end, the first end coupled to the level shifting stage and the second end for coupling to a second reference voltage. In addition, the circuit arrangement may include a bypass circuit element connected in parallel to the load. The bypass circuit element may be configured to allow current to flow through upon application of an external voltage for bypassing the load.

Abstract translation: 在各种实施例中，可以提供电路装置。 电路装置可以包括被配置为耦合到第一参考电压的电平移位级，电平移位级具有输出节点。 电路装置还可以包括与电平转换级电连接的第一输入电极。 电路装置还可以包括与电平转换级电连接的第二输入电极。 电路装置还可以包括具有第一端和第二端的负载，第一端耦合到电平移位级，第二端耦合到第二参考电压。 另外，电路装置可以包括与负载并联连接的旁路电路元件。 旁路电路元件可以被配置为允许电流在施加用于绕过负载的外部电压时流过。