公开(公告)号：US20230387920A1

公开(公告)日：2023-11-30

申请号：US17751679

申请日：2022-05-24

Applicant: Airoha Technology Corp.

Inventor： Heng-Chih Lin ,  Shu-Yu Lin

IPC: H03L7/091 ,  H03L7/099 ,  H03L1/02

CPC classification number: H03L7/091 ,  H03L7/099 ,  H03L1/02

Abstract: A phase-locked loop (PLL) circuit includes a PLL core circuit, at least one lookup table, and a control circuit. The PLL core circuit generates an output clock under an open-loop calibration phase and a closed-loop calibration phase. The control circuit loads PLL parameters that are derived from the at least one lookup table to the PLL core circuit, performs open-loop calibration upon a first part of the PLL parameters under the open-loop calibration phase of the PLL core circuit, and performs closed-loop calibration upon a second part of the PLL parameters under the closed-loop calibration phase of the PLL core circuit.

公开(公告)号：US20230387919A1

公开(公告)日：2023-11-30

申请号：US17751675

申请日：2022-05-24

Applicant: Airoha Technology Corp.

Inventor： Heng-Chih Lin ,  Shu-Yu Lin

IPC: H03L7/089 ,  H03L7/091

CPC classification number: H03L7/0898 ,  H03L7/091

Abstract: A charge pump of a phase-locked loop (PLL) circuit includes a current source circuit, a current sink circuit, and a biasing circuit. The biasing circuit includes a current digital-to-analog converter (IDAC) and a low-pass filter (LPF). The IDAC provides a reference current in response to a current value setting, wherein a first voltage is established due to the reference current. The LPF applies low-pass filtering to the first voltage to generate a filter output as a second voltage, wherein bias voltages of the current source circuit and the current sink circuit are controlled by the second voltage.

公开(公告)号：US20230361791A1

公开(公告)日：2023-11-09

申请号：US17737046

申请日：2022-05-05

Applicant: Airoha Technology Corp.

Inventor： Yu-Hua Liu ,  Shu-Yu Lin

IPC: H04B1/00 ,  H04B1/40 ,  H04K3/00

CPC classification number: H04B1/0057 ,  H04B1/40 ,  H04K3/22

Abstract: A sub-circuit of a reconfigurable wireless receiver includes a down-conversion circuit and a plurality of filters. The down-conversion circuit applies down-conversion to a first signal, and generates and outputs a plurality of second signals each derived from down-converting the first signal. The filters are coupled to the down-conversion circuit, and apply filtering to the second signals for generating a plurality of filter outputs, respectively, wherein the filters includes a first filter and a second filter, and the first filter and the second filter have different filter architecture.