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公开(公告)号:US20100260428A1
公开(公告)日:2010-10-14
申请号:US12725300
申请日:2010-03-16
申请人: Akira UENO , Keisuke Nakazono , Yoshinobu Tanaka
发明人: Akira UENO , Keisuke Nakazono , Yoshinobu Tanaka
CPC分类号: H04N19/423 , H04N19/80
摘要: An image processing apparatus includes image processors and a margin storing buffer. The image processors read an input image data from a frame memory for each image data of a plurality of block lines each having a first number of pixels along the columns and a second number of pixels along the rows. The margin storing buffer stores the image data of the margin portion used also in the image processing of the image data of the next block line, among the image data of the present block line input to each of the image processors. Each of the image processors performs the image processing on an image data including the image data of the present block line and the image data of the margin portion, at the time of image processing on the image data of the next block line.
摘要翻译: 图像处理装置包括图像处理器和边缘存储缓冲器。 图像处理器从帧存储器读取每个具有沿列的第一数量像素的多个块行的每个图像数据的输入图像数据和沿行的第二数量的像素。 在输入到每个图像处理器的当前块行的图像数据中,边缘存储缓冲器还存储用于下一个块行的图像数据的图像处理中的边缘部分的图像数据。 在对下一个块行的图像数据进行图像处理时,每个图像处理器对包括当前块行的图像数据和边缘部分的图像数据的图像数据执行图像处理。
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公开(公告)号:US20100325375A1
公开(公告)日:2010-12-23
申请号:US12818571
申请日:2010-06-18
申请人: Akira UENO , Naruyasu KOBAYASHI
发明人: Akira UENO , Naruyasu KOBAYASHI
IPC分类号: G06F12/00
CPC分类号: G06F13/1626
摘要: A memory control unit sequentially performs access requests to a plurality of banks A to D for a high-speed module 1 according to settings of the high-speed module, and subsequently performs an access request to a bank for a low-speed module after completion of a process of consecutive access requests for the high-speed module. In this case, an initial address that the high-speed module is to access is set to an address location for accessing a bank different from the low-speed module.
摘要翻译: 存储器控制单元根据高速模块的设置顺序地执行对高速模块1的多个存储体组A至D的访问请求,并且随后在完成后对低速模块的存储体执行访问请求 对高速模块的连续访问请求的过程。 在这种情况下,高速模块要访问的初始地址被设置为访问不同于低速模块的存储体的地址位置。
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公开(公告)号:US20100325338A1
公开(公告)日:2010-12-23
申请号:US12815742
申请日:2010-06-15
申请人: Akira UENO , Naruyasu Kobayashi
发明人: Akira UENO , Naruyasu Kobayashi
CPC分类号: G06F13/1647
摘要: First and second modules output a predetermined volume of data at a certain rate around the same time. A setting is made so that transfer addresses from the second module are shifted relative to transfer addresses from the first module such that a bank to which the first module issues a data transfer request is in a position separate from a bank to which the second module issues a data transfer request.
摘要翻译: 第一和第二模块在同一时间以一定速率输出预定量的数据。 进行设置,使得来自第二模块的传送地址相对于来自第一模块的传送地址移动,使得第一模块发出数据传输请求的存储体与第二模块发布的存储体分离 数据传输请求。
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