摘要:
A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing. A status manager (20) handles actions coming from other task units and builds actions to be sent to other task units
摘要:
In a remote computer, a method for providing a file comprises the steps of receiving a request for this file, identifying this file as being stored in a distant server, requesting the distance server to send the file, identifying this file as being used, and forwarding this file. Further, in a local server, a method for transferring a file from a home server comprises the steps of receiving a request for this file, this request comprising the home server identification, checking that this file is not locally stored, requesting this file to the home server, identifying the file as being locally used, and forwarding this file.
摘要:
According to the invention, a device for transferring data between two workstations connected to a network is provided. This device comprises means for distributing data among a plurality of links of the network. Preferentially, the device comprises a dual-port memory for storing the data. In a preferred embodiment, the device further comprises a high speed interface for transmitting data from a workstation to the memory, associated with each link, a low speed interface for transmitting a part of the data from the memory to this link, and a controller for monitoring the data flow between the workstation and the plurality of links, by controlling the memory and the interfaces.
摘要:
A FISU frame handler which is connected between an adapter and a SS7 low speed network. For each FISU frames transmitted or received in the adapter, an interrupt is generated to a processor located in the adapter. In order to diminish the number of processor interruptions, the FISU frames are externally processed by the FISU frame handler by discarding repeated FISU frames transmitted from the network so as to generate idle state signals to the adapter and by converting idle state signals received from the adapter into repetitive FISU frames to transmit them to the network without interrupting the processor. In order to perform both functions, the FISU frame handler comprises two dedicated hardware units which operate according to specific methods.
摘要:
A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing. A status manager (20) handles actions coming from other task units and builds actions to be sent to other task units.
摘要:
A system and method for performing interleaved packet processing. A packet includes a source address bit pattern and a destination address bit pattern that are processed by a task processor in accordance with a data tree. A first bank of registers is utilized to load an instruction to be executed by the task processor at nodes of the data tree in accordance with the source address bit pattern. A second bank of registers is utilized for loading an instruction to be executed by the task processor at nodes of the data tree in accordance with the destination address bit pattern. A task scheduler enables the first bank of registers to transfer an instruction loaded therein for processing by the task processor only during even time cycles and for enabling the second bank of registers to transfer an instruction loaded therein for processing by the task processor only during odd time cycles.
摘要:
The invention relates to a Universal Serial Bus (USB) with two wireless communication hubs (USB hubs). One of these hubs is connected to a first host computer, and both USB hubs are connected to a plurality of I/O devices. Each USB hub includes a wireless adapter and an antenna connected to the wireless adapter. The wireless adapter of each USB hub comprises a transmitting/receiving unit for transmitting data via the antenna to the wireless adapter of the other USB hub or receiving data via the antenna from the wireless adapter of the other USB hub. The wireless adapter also comprises a wireless dual port, which is automatically configured upstream or downstream when the first host computer is connected to one of the USB hubs.
摘要:
Hardware device for parallel processing a determined instruction of a set of instructions having a same format defining operand fields and other data fields, the execution of this determined instruction being represented as an algorithm comprising a plurality of processes, the processing of which depending on decisions. Such a device comprises means (22-30) for activating the processing of one or several processes (32-38) determined by the operand fields of the instruction, decision macroblocks (12-20) each being associated with a specific instruction of the set of instructions, only one decision marcoblock being selected by the determined instruction in order to determine which are the process(es) to be activated for executing the determined instruction.
摘要:
A telecommunication node for an Asynchronous Transfer Mode (ATM) telecommunication network performs Segmentation and Reassembly (SAR) of ATM cells. The SAR particularly provides Virtual Channel Identifier (VCI) and Virtual Path Identifier (VPI) translation and further provides a Direct Memory Access (DMA) for accessing an external storage. When the VCI and VPI identifiers are representative of an Error Code Correcting (ECC) procedure to be carried out in the local mode, the SAR circuit performs a first DMA access which is decoded by an address decoder. Conversely, when no ECC procedure is locally required, the SAR decodes the VCI and VPI and performs a second DMA access which is also decoded by the address decoder. The latter decoding is then used by a Reed-Solomon Coder and Decoder for possibly performing an error correcting procedure on the ATM message formed by the ATM cells being processed.
摘要:
Method of reinitializing dictionaries in a data transmission system using data compression having a transmit device and a receive device, and in which strings of characters have to be transmitted in a compressed form, the transmit device having a transmit dictionary storing codewords associated with the strings of characters which are transmitted instead of the strings of characters, the receive device having a receive dictionary storing codewords associated with the strings of characters, and both dictionaries being updated each time a new string of characters has to be transmitted so that the contents of the dictionaries remain identical. This method saves at least the addresses of the parts of the transmit or receive dictionary which have to be modified by a dictionary updating operation, builds a check message based upon the contents of the transmit dictionary updated by the dictionary updating operation, transmits the check message from the transmit device to the receive device, and then deletes in both dictionaries the parts which are determined by the saved addresses in the event that the check message does not correspond to the contents of the updated receive dictionary. This enables both dictionaries to be reinitialized in an intermediate state without being reset.