公开(公告)号：US06184665B2

公开(公告)日：2001-02-06

申请号：US09174867

申请日：1998-10-19

申请人： Alberto Salina ,  Donatella Brambilla

发明人： Alberto Salina ,  Donatella Brambilla

IPC分类号： G05F140

CPC分类号： H02P25/034 ,  H02P7/04

摘要： In a current mode pulse width modulation (PWM) integrated drive system having an external load, a switched-capacitor amplifier and a sample & hold stage connected in cascade form a current sensing amplifier for a control loop. The current sensing amplifier overcomes resistive mismatchings, thus permitting a scaling down of the supply voltage with high precision for the integrated drive system.

摘要翻译： 在具有外部负载的电流模式脉宽调制（PWM）集成驱动系统中，开关电容放大器和级联连接的采样和保持级形成用于控制回路的电流感测放大器。 电流感测放大器克服了电阻失配，从而允许集成驱动系统以高精度降低电源电压。

公开(公告)号：US6023143A

公开(公告)日：2000-02-08

申请号：US109022

申请日：1998-07-01

申请人： Alberto Salina ,  Donatella Brambilla

发明人： Alberto Salina ,  Donatella Brambilla

IPC分类号： H02P7/29 ,  H02P7/292 ,  H02P7/00

CPC分类号： G11B5/5547 ,  H02P25/034 ,  H02P7/29 ,  H02P7/292

摘要： A mixed mode PWM/Linear driving system for at least one inductive-resistive (L-R) actuator as a function of operating conditions thereof includes a first full bridge power stage including four power switching devices arranged in pairs for being driven in phase opposition. The system also includes a pulse width modulation (PWM) converter for producing a PWM signal directly driving the first full bridge power stage during a PWM mode operating phase. A second full bridge power stage also comprises four power switching devices of different electrical characteristics from the power switching devices of the first full bridge power stage. The system further includes a pair of amplifiers connected to respective pairs of power switching devices of the second full bridge power stage for driving same in phase opposition during a linear mode operating phase. A switch is provided for switching between the PWM mode operating phase and the linear mode operating phase.

摘要翻译： 作为其工作条件的函数的至少一个电感电阻（L-R）致动器的混合模式PWM /线性驱动系统包括第一全桥功率级，其包括成对布置的四个功率开关器件，用于相位驱动。 该系统还包括用于在PWM模式操作阶段期间产生直接驱动第一全桥功率级的PWM信号的脉宽调制（PWM）转换器。 第二全桥功率级还包括与第一全桥功率级的功率开关器件不同的电特性的四个功率开关器件。 该系统还包括连接到第二全桥功率级的相应成对的功率开关装置的一对放大器，用于在线性模式操作阶段期间以相位相对的方式驱动它们。 提供用于在PWM模式操作阶段和线性模式操作阶段之间切换的开关。

公开(公告)号：US08400820B2

公开(公告)日：2013-03-19

申请号：US12974569

申请日：2010-12-21

申请人： Danilo Rimondi ,  Donatella Brambilla ,  Rita Zappa ,  Carolina Selva

发明人： Danilo Rimondi ,  Donatella Brambilla ,  Rita Zappa ,  Carolina Selva

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： An embodiment of a memory device includes a plurality of memory cells; each memory cell includes a latch adapted to store an information bit. Said latch includes a first logic gate including a first input terminal and a first output terminal and a second logic gate including a second input terminal and a second output terminal. Said first input terminal is connected to said second output terminal and said first output terminal is connected to said second input terminal. The memory device further includes reading and writing means adapted to perform a read operation or a write operation of the information bit. Said first logic gate includes a pull-up branch coupled between a terminal for providing a supply voltage and the first output terminal, and a pull-down branch coupled between the first output terminal and a terminal for providing a reference voltage. Said second logic gate includes a pull-up branch coupled between a terminal for providing the supply voltage and the second output terminal, and a pull-down branch coupled between the second output terminal and a terminal for providing the reference voltage. Said memory device includes variation means adapted to selectively vary a gain factor of at least one between the pull-down branch and the pull-up branch of said first logic gate and second logic gate depending on the operation performed by the reading and writing means.

摘要翻译： 存储器件的实施例包括多个存储器单元; 每个存储器单元包括适于存储信息位的锁存器。 所述锁存器包括包括第一输入端和第一输出端的第一逻辑门和包括第二输入端和第二输出端的第二逻辑门。 所述第一输入端连接到所述第二输出端，所述第一输出端连接到所述第二输入端。 存储装置还包括适于执行信息位的读取操作或写入操作的读取和写入装置。 所述第一逻辑门包括耦合在用于提供电源电压的端子和第一输出端子之间的上拉支路，以及耦合在第一输出端子和用于提供参考电压的端子之间的下拉支路。 所述第二逻辑门包括耦合在用于提供电源电压的端子和第二输出端子之间的上拉支路，以及耦合在第二输出端子和用于提供参考电压的端子之间的下拉支路。 所述存储器件包括适于根据读取和写入装置执行的操作，选择性地改变所述第一逻辑门和第二逻辑门的​​下拉支路和上拉支路之间的至少一个的增益因子的变化装置。