公开(公告)号：US06424557B1

公开(公告)日：2002-07-23

申请号：US09728571

申请日：2000-11-30

申请人： Alessandro Camera ,  Paolo Sandri ,  Ignazio Bellomo ,  Filippo Marino

发明人： Alessandro Camera ,  Paolo Sandri ,  Ignazio Bellomo ,  Filippo Marino

IPC分类号： G11C1700

摘要： An integrated device comprises at least one circuit element and a plurality of trimming elements which can be connected selectively to the at least one circuit element in order to achieve a predetermined tolerance of a characteristic parameter of the at least one circuit element; the integrated device includes a plurality of electronic switches, each of which can be switched between a first state and a second state in which it activates and deactivates a corresponding one of the trimming elements, respectively, and a memory for storing an indication of the states of the electronic switches and for operating each electronic switch in the first state or in the second state according to the indication stored.

公开(公告)号：US06381185B2

公开(公告)日：2002-04-30

申请号：US09782969

申请日：2001-02-14

申请人： Alessandro Camera ,  Paolo Sandri ,  Ignazio Bellomo ,  Albino Pidutti

发明人： Alessandro Camera ,  Paolo Sandri ,  Ignazio Bellomo ,  Albino Pidutti

IPC分类号： G11C700

CPC分类号： G11C29/50004 ,  G06F2201/81 ,  G11C16/04 ,  G11C29/50

摘要： A method for testing a programmable, nonvolatile memory including a matrix of memory cells is provided. A plurality of memory cells are programmed. The programmed memory cells are addressed in succession to identify a lowest of threshold voltage levels. The addressing for each memory location includes applying a selection voltage that is lower than the lowest threshold voltage level corresponding to a memory location currently being addressed. The bits are read from the programmed memory cells for the memory location currently being addressed. The reading is repeated while progressively changing the selection voltage supplied to the word line corresponding to the memory location currently being addressed until it is detected that at least one of the bits of the memory location currently being addressed has switched from a first logic level corresponding to a reading of a programmed memory cell to a second logic level corresponding to a reading of a non-programmed memory cell. The low threshold voltage level is compared in the memory location currently being addressed as determined in the reading with a stored value corresponding to the lowest of the low threshold voltages of the memory locations previously addressed.

摘要翻译： 提供了一种用于测试包括存储器单元矩阵的可编程非易失性存储器的方法。 多个存储单元被编程。 编程的存储器单元被连续寻址以识别阈值电压电平的最低值。 每个存储器位置的寻址包括施加低于对应于当前被寻址的存储器位置的最低阈值电压电平的选择电压。 这些位从当前正在寻址的存储器位置的已编程存储单元读取。 重复读取，同时逐渐改变提供给对应于当前正被寻址的存储器位置的字线的选择电压，直到检测到当前被寻址的存储器位置中的至少一个位已经从对应于 将编程的存储器单元读取到对应于非编程存储器单元的读取的第二逻辑电平。 在当前正在寻址的存储器位置中，在读取中确定的低阈值电压电平与对应于先前寻址的存储器位置的最低阈值电压的存储值进行比较。

公开(公告)号：US06772379B1

公开(公告)日：2004-08-03

申请号：US09710089

申请日：2000-11-10

申请人： Alessandro Camera ,  Ignazio Bellomo ,  Paolo Sandri

发明人： Alessandro Camera ,  Ignazio Bellomo ,  Paolo Sandri

IPC分类号： G11C2900

CPC分类号： G11C29/50016 ,  G11C16/04 ,  G11C29/50

摘要： An apparatus for verifying the data retention in a non-volatile memory is described which comprises at least one multiplexer and at least one shift register. The multiplexer and the at least one shift register are disposed so that the data of the non-volatile memory are in input to the multiplexer the output of which is in turn in input to the at least one shift register. The apparatus comprises a logical circuitry which by suitable commands controls the data transfer from said multiplexer to said at least one shift register, the data loading and the output data shifting in said at least one shift register.

摘要翻译： 描述了一种用于验证非易失性存储器中的数据保持的装置，其包括至少一个多路复用器和至少一个移位寄存器。 多路复用器和至少一个移位寄存器被布置成使得非易失性存储器的数据被输入到多路复用器，其输出又被输入到至少一个移位寄存器。 该装置包括逻辑电路，其通过适当的命令控制从所述多路复用器到所述至少一个移位寄存器的数据传输，数据加载和输出数据在所述至少一个移位寄存器中移位。

公开(公告)号：US06396251B2

公开(公告)日：2002-05-28

申请号：US09800759

申请日：2001-03-06

申请人： Giulio Corva ,  Alessandro Camera ,  Ignazio Bellomo

发明人： Giulio Corva ,  Alessandro Camera ,  Ignazio Bellomo

IPC分类号： G05F156

CPC分类号： H02M3/1563 ,  H02M3/158

摘要： The invention relates to a control circuit for a hysteretic switching voltage regulator, which comprises a logic circuit driving an output stage; a hysteresis comparator comparing the voltage value at the output of the regulator with a reference voltage; a current sensor for sensing, through a comparator, the current drain of a load connected to the output of the regulator. This control circuit further comprises a device for adjusting the hysteresis range of the hysteresis comparator, and a hysteresis frequency sensing and controlling logic portion connected to the output of the hysteresis comparator, the logic portion acting on the frequency adjusting device.

摘要翻译： 本发明涉及一种用于迟滞开关电压调节器的控制电路，其包括驱动输出级的逻辑电路; 比较调节器输出端的电压值与参考电压的滞后比较器; 电流传感器，用于通过比较器感测连接到调节器的输出的负载的电流消耗。 该控制电路还包括用于调节滞后比较器的滞后范围的装置，以及连接到滞后比较器的输出的滞后频率感测和控制逻辑部分，逻辑部分作用在频率调节装置上。

公开(公告)号：US06362664B1

公开(公告)日：2002-03-26

申请号：US09302720

申请日：1999-04-30

申请人： Alessandro Camera ,  Paolo Sandri

发明人： Alessandro Camera ,  Paolo Sandri

IPC分类号： H03K300

CPC分类号： H03K19/01721 ,  H03K19/00315

摘要： An active pull-up circuit for connection to an input pin that receives high and low logic level signals and a high voltage signal whose level is higher than the high logic level. The active pull-up circuit includes a pull-up circuit that is coupled between the input pin and a voltage supply line, and a breaking circuit that is coupled between the pull-up circuit and the voltage supply line. The pull-up circuit selectively brings the input pin to the level of the voltage supply line, and the breaking circuit operates to inhibit the pull-up circuit when the high voltage signal is on the input pin. In a preferred embodiment, the breaking circuit inhibits the pull-up circuit by electrically isolating the pull-up circuit from the voltage supply line. A method for selectively pulling-up an input node is also provided. According to the method, the input node is pulled-up to the level of a supply voltage at least when the input node receives a floating voltage, and such pulling-up of the input node is inhibited at least when the input node receives a high voltage signal whose level is higher than the level of the supply voltage.

摘要翻译： 用于连接到输入引脚的有源上拉电路，其接收高和低逻辑电平信号以及电平高于高逻辑电平的高电压信号。 有源上拉电路包括耦合在输入引脚和电压供应线之间的上拉电路，以及耦合在上拉电路和电压供应线之间的断路电路。 上拉电路有选择地将输入引脚输入到电源线的电平，当高电压信号在输入引脚上时，断路电路可以抑制上拉电路。 在优选实施例中，断路电路通过将上拉电路与电压供应线电隔离来阻止上拉电​​路。 还提供了用于选择性地提升输入节点的方法。 根据该方法，输入节点至少在输入节点接收浮动电压时被上拉至电源电压的电平，并且至少当输入节点接收到高电平时，输入节点的上拉被禁止 电平高于电源电压的电压信号。