公开(公告)号：US5905855A

公开(公告)日：1999-05-18

申请号：US807542

申请日：1997-02-28

申请人： Alex Klaiber ,  Robert Bedichek ,  David Keppel

发明人： Alex Klaiber ,  Robert Bedichek ,  David Keppel

IPC分类号： G06F11/28 ,  G06F11/16 ,  G06F11/34 ,  G06F11/36 ,  G06F11/26

CPC分类号： G06F11/3688 ,  G06F11/1641

摘要： A computer implemented process for detecting errors in computer systems including the steps of executing sequences of instructions of a software program on each of a reference system and a test system, detecting and recording state of the reference system and the test system at comparable points in the execution of the program, and comparing the detected state of the reference system and the test system at selectable comparable points in the sequence of instructions including the end of the sequence of instructions. In a particular embodiment, the execution of portions of the sequence of instructions between selectable comparable points on each of the reference system and the test system is automatically replayed if a difference in compared state of the systems is detected.

摘要翻译： 一种用于检测计算机系统中的错误的计算机实现过程，包括以下步骤：在参考系统和测试系统中的每一个上执行软件程序的指令序列，在参考系统和测试系统的相似点处检测和记录参考系统和测试系统的状态 执行程序，以及在包括指令序列的结束的指令序列中的可选择的可比较点处比较检测到的参考系统和测试系统的状态。 在特定实施例中，如果检测到系统的比较状态的差异，则在参考系统和测试系统中的每个参考系之间的可选择可比点之间的指令序列的部分的执行被自动重放。

公开(公告)号：US07617088B1

公开(公告)日：2009-11-10

申请号：US11110085

申请日：2005-01-18

申请人： Robert Bedichek ,  David Keppel ,  John Banning

发明人： Robert Bedichek ,  David Keppel ,  John Banning

IPC分类号： G06F9/455

CPC分类号： G06F9/3017

摘要： In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.

摘要翻译： 在将指令从目标指令集转换为主机指令集的计算机中，确定与早期转换相关联的目标指令的转换的有效性的方法，包括以下步骤：测试要执行的目标指令的存储器地址 目标指令的译码的目标指令的存储器地址的副本，如果地址比较则执行转换，如果地址不比较则产生异常。

公开(公告)号：US08418153B2

公开(公告)日：2013-04-09

申请号：US12578500

申请日：2009-10-13

申请人： Robert Bedichek ,  Linus Torvalds ,  David Keppel

发明人： Robert Bedichek ,  Linus Torvalds ,  David Keppel

IPC分类号： G06F9/455 ,  G06F9/46

CPC分类号： G06F9/3017 ,  G06F9/3861 ,  G06F9/45516

摘要： A method for executing a target application on a host processor including the steps of translating each target instruction being to be executed into host instructions, storing the translated host instructions, executing the translated host instructions, responding to an exception during execution of a translated instruction by rolling back to a point in execution at which correct state of a target processor is known, and interpreting each target instruction in order from the point in execution at which correct state of a target processor is known.

摘要翻译： 一种用于在主处理器上执行目标应用程序的方法，包括以下步骤：将要执行的每个目标指令转换成主机指令，存储所翻译的主机指令，执行转换的主机指令，在执行翻译指令期间响应异常 回滚到目标处理器的正确状态已知的执行点，并且从目标处理器的正确状态已知的执行点起按顺序解释每个目标指令。

公开(公告)号：US20100262955A1

公开(公告)日：2010-10-14

申请号：US12578500

申请日：2009-10-13

申请人： Robert Bedichek ,  Linus Torvalds ,  David Keppel

发明人： Robert Bedichek ,  Linus Torvalds ,  David Keppel

IPC分类号： G06F9/455 ,  G06F9/45

CPC分类号： G06F9/3017 ,  G06F9/3861 ,  G06F9/45516

摘要： A method for executing a target application on a host processor including the steps of translating each target instruction being to be executed into host instructions, storing the translated host instructions, executing the translated host instructions, responding to an exception during execution of a translated instruction by rolling back to a point in execution at which correct state of a target processor is known, and interpreting each target instruction in order from the point in execution at which correct state of a target processor is known.

摘要翻译： 一种用于在主处理器上执行目标应用程序的方法，包括以下步骤：将要执行的每个目标指令转换成主机指令，存储所翻译的主机指令，执行转换的主机指令，在执行翻译指令期间响应异常 回滚到目标处理器的正确状态已知的执行点，并且从目标处理器的正确状态已知的执行点起按顺序解释每个目标指令。

公开(公告)号：US06415379B1

公开(公告)日：2002-07-02

申请号：US09417981

申请日：1999-10-13

申请人： David Keppel ,  Robert Cmelik ,  Robert Bedichek

发明人： David Keppel ,  Robert Cmelik ,  Robert Bedichek

IPC分类号： G06F9455

CPC分类号： G06F9/45504

摘要： A method of maintaining translation context for instructions translated from instructions designed for a target microprocessor to run on a host microprocessor including storing translation context related to each translated host instruction, indicating a translation context for host instructions presently being executed by the host processor, comparing translation context stored for a next host instruction with the translation context for a host instruction presently being executed, executing the next host instruction if the translation context of the next host instruction and the presently executing host instruction compare, and searching for an instruction with translation context which compares to the translation context of the host instruction presently executing if the translation context of the next host instruction and the presently executing host instruction do not compare.

摘要翻译： 一种维护用于由目标微处理器设计的指令在主机微处理器上运行的指令的转换上下文的方法，包括存储与每个转换的主机指令相关的转换上下文，指示当前由主处理器执行的主机指令的转换上下文， 如果当前正在执行的主机指令的翻译上下文存储下一个主机指令的上下文，则如果下一个主机指令和当前执行的主机指令的转换上下文相比较，则执行下一个主机指令，并且搜索具有翻译上下文的指令 如果下一个主机指令和当前执行的主机指令的转换上下文不进行比较，则与当前执行的主机指令的转换上下文进行比较。

公开(公告)号：US07761857B1

公开(公告)日：2010-07-20

申请号：US09417332

申请日：1999-10-13

申请人： Robert Bedichek ,  Linus Torvalds ,  David Keppel

发明人： Robert Bedichek ,  Linus Torvalds ,  David Keppel

IPC分类号： G06F9/455

CPC分类号： G06F9/3017 ,  G06F9/3861 ,  G06F9/45516

摘要： A method for executing a target application on a host processor including the steps of translating each target instruction being to be executed into host instructions, storing the translated host instructions, executing the translated host instructions, responding to an exception during execution of a translated instruction by rolling back to a point in execution at which correct state of a target processor is known, and interpreting each target instruction in order from the point in execution at which correct state of a target processor is known.

摘要翻译： 一种用于在主处理器上执行目标应用程序的方法，包括以下步骤：将要执行的每个目标指令转换成主机指令，存储所翻译的主机指令，执行转换的主机指令，在执行翻译指令期间响应异常 回滚到目标处理器的正确状态已知的执行点，并且从目标处理器的正确状态已知的执行点起按顺序解释每个目标指令。

公开(公告)号：US06845353B1

公开(公告)日：2005-01-18

申请号：US09471447

申请日：1999-12-23

申请人： Robert Bedichek ,  David Keppel ,  John Banning

发明人： Robert Bedichek ,  David Keppel ,  John Banning

IPC分类号： G06F9/44 ,  G06F9/455 ,  G06F9/46 ,  G06F11/25 ,  G06F12/04

CPC分类号： G06F9/3017

摘要： In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.

摘要翻译： 在将指令从目标指令集转换为主机指令集的计算机中，确定与早期转换相关联的目标指令的转换的有效性的方法，包括以下步骤：测试要执行的目标指令的存储器地址 目标指令的译码的目标指令的存储器地址的副本，如果地址比较则执行转换，如果地址不比较则产生异常。

公开(公告)号：US06594821B1

公开(公告)日：2003-07-15

申请号：US09539987

申请日：2000-03-30

申请人： John Banning ,  H. Peter Anvin ,  Robert Bedichek ,  Guillermo J. Rozas ,  Andrew Shaw ,  Linus Torvalds ,  Jason Wilson

发明人： John Banning ,  H. Peter Anvin ,  Robert Bedichek ,  Guillermo J. Rozas ,  Andrew Shaw ,  Linus Torvalds ,  Jason Wilson

IPC分类号： G06F9455

CPC分类号： G06F9/3808 ,  G06F9/3812

摘要： A method for maintaining consistency between translated host instructions and target instructions from which the host instructions have been translated including the steps of maintaining a copy of a target instruction for which a translated host instruction have been made, comparing the copy of the target instruction with a target instruction at a memory address at which the target instruction from which the copy was made was stored when translated, disabling the translated host instruction if the copy of the target instruction is not the same as the target instruction at the memory address, and executing the translated host instruction if the copy of the target instruction is the same as the target instruction at the memory address.

摘要翻译： 一种用于保持转换的主机指令与已经被转换了主机指令的目标指令之间的一致性的方法，包括维护已经进行转换的主机指令的目标指令的副本的步骤，将目标指令的副本与 在翻译时存储复制的目标指令的存储器地址处的目标指令，如果目标指令的副本与存储器地址处的目标指令不相同，则禁用转换的主机指令，并执行 如果目标指令的副本与存储器地址上的目标指令相同，则转换主机指令。

公开(公告)号：US20120036502A1

公开(公告)日：2012-02-09

申请号：US13021609

申请日：2011-02-04

申请人： John Banning ,  H. Peter Anvin ,  Robert Bedichek ,  Guillermo J. Rozas ,  Andrew Shaw ,  Linus Torvalds ,  Jason Wilson

发明人： John Banning ,  H. Peter Anvin ,  Robert Bedichek ,  Guillermo J. Rozas ,  Andrew Shaw ,  Linus Torvalds ,  Jason Wilson

IPC分类号： G06F9/455

CPC分类号： G06F9/3808 ,  G06F9/3812

摘要： In one embodiment, after translating a plurality of target instructions from a target memory location into a plurality of host instructions, a write operation to a target memory portion which includes said target memory location is detected. In response to the detecting, a copy of the target instructions is stored in a host memory. In response to an attempt to execute the host instructions, the copy is compared with a plurality of current target instructions presently stored in the target memory location. Further, in response to a mismatch based on the comparison, the host instructions are disabled.

摘要翻译： 在一个实施例中，在将多个目标指令从目标存储器位置翻译成多个主机指令之后，检测到包括所述目标存储器位置的目标存储器部分的写入操作。 响应于检测，将目标指令的副本存储在主机存储器中。 响应于尝试执行主机指令，将该副本与当前存储在目标存储器位置中的多个当前目标指令进行比较。 此外，响应于基于比较的不匹配，主机指令被禁用。

公开(公告)号：US07904891B2

公开(公告)日：2011-03-08

申请号：US12177836

申请日：2008-07-22

申请人： John Banning ,  H. Peter Anvin ,  Robert Bedichek ,  Guillermo J. Rozas ,  Andrew Shaw ,  Linus Torvalds ,  Jason Wilson

发明人： John Banning ,  H. Peter Anvin ,  Robert Bedichek ,  Guillermo J. Rozas ,  Andrew Shaw ,  Linus Torvalds ,  Jason Wilson

IPC分类号： G06F9/455

CPC分类号： G06F9/3808 ,  G06F9/3812

摘要： In one embodiment, after translating a plurality of target instructions from a target memory location into a plurality of host instructions, a write operation to a target memory portion which includes said target memory location is detected. In response to the detecting, a copy of the target instructions is stored in a host memory. In response to an attempt to execute the host instructions, the copy is compared with a plurality of current target instructions presently stored in the target memory location. Further, in response to a mismatch based on the comparison, the host instructions are disabled.

摘要翻译： 在一个实施例中，在将多个目标指令从目标存储器位置翻译成多个主机指令之后，检测到包括所述目标存储器位置的目标存储器部分的写入操作。 响应于检测，将目标指令的副本存储在主机存储器中。 响应于尝试执行主机指令，将该副本与当前存储在目标存储器位置中的多个当前目标指令进行比较。 此外，响应于基于比较的不匹配，主机指令被禁用。