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公开(公告)号：US06941533B2
公开(公告)日：2005-09-06
申请号：US10277398
申请日：2002-10-21
CPC分类号： G06F17/5077 , G06F1/10 , G06F17/5045 , G06F2217/62
摘要： A method of synthesizing a clock tree for reducing peak power in an integrated circuit design includes partitioning a circuit design into a set of memory cells and a set of non-memory cells, partitioning the set of memory cells into segments, constructing a first clock tree having a first root vertex with a corresponding initial skew for each of the segments, constructing a second clock tree having a second root vertex with a corresponding initial skew for the set of non-memory cells, delay balancing the first root vertex and the second vertex clock tree, and inserting a clock buffer at a midpoint between the first root vertex and the second root vertex.
摘要翻译： 一种合成用于降低集成电路设计中的峰值功率的时钟树的方法包括将电路设计划分成一组存储器单元和一组非存储器单元，将该组存储器单元分成段，构建第一时钟树 具有对于每个段具有对应的初始偏移的第一根顶点，构造具有第二根顶点的第二时钟树，该第二根顶点具有用于所述非存储器单元组的对应的初始偏移，延迟平衡所述第一根顶点和所述第二顶点 时钟树，并且在第一根顶点和第二根顶点之间的中点处插入时钟缓冲器。
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">2.发明授权Physical design automation system and process for designing integrated circuit chip using "chessboard" and "jiggle" optimization 失效物理设计自动化系统和使用“棋盘”和“抖动”优化设计集成电路芯片的过程
公开(公告)号：US6038385A
公开(公告)日：2000-03-14
申请号：US609397
申请日：1996-03-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A cell placement for an integrated circuit chip is divided into two "chessboard" patterns or "jiggles". Each pattern resembles a chessboard in that it consists of alternating regions of different types or "colors" such that no region of a given color has an edge common with another region of the same color. The jiggles are offset relative to each other such that the regions of one jiggle partially overlap at least two regions of the other jiggle. A placement improvement operation such as simulated annealing is performed sequentially for each color of each jiggle. During each operation, a plurality of parallel processors operate on the regions simultaneously using a previous copy of the entire chip, with one processor being assigned to one or more regions. At the end of each operation, the copy of the chip is updated. The chessboard patterns eliminate unproductive cell moves resulting from adjacent regions having a common edge. The jiggles enable cells to move to their optimal positions from their initial region to any other region on the chip. The regions can have rectangular, triangular or hexagonal shapes.
摘要翻译： 集成电路芯片的单元布局分为两个“棋盘”图案或“跳棋”。 每个图案类似于棋盘，其由不同类型或“颜色”的交替区域组成，使得给定颜色的区域不具有与相同颜色的另一区域相同的边缘。 跳块相对于彼此偏移，使得一个颤动的区域部分地与另一个摇摆的至少两个区域重叠。 针对每个抖动的每个颜色顺序地执行诸如模拟退火的放置改善操作。 在每个操作期间，多个并行处理器使用整个芯片的先前副本同时在该区域上操作，一个处理器被分配给一个或多个区域。 在每个操作结束时，更新芯片的副本。 棋盘图案消除由具有共同边缘的相邻区域产生的非生产性细胞移动。 这些跳跃使得电池从它们的初始区域移动到其最佳位置到芯片上的任何其它区域。 这些区域可以具有矩形，三角形或六边形形状。
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公开(公告)号：US06292924B1
公开(公告)日：2001-09-18
申请号：US08964997
申请日：1997-11-05
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Designing of the IC's require meeting real-world constraints such as minimization of the circuit area, minimization of wire length within the circuit, and minimization of the time the IC requires to perform its function, referred to as the IC delay. In order to design circuits to meet a given set of requirements, each signal path of the circuit must be analyzed. Because of the large number of the cells and the complex connections, the number of paths is very large and requires much computing power to analyze. Also, some of the paths are not important for the purposes of the operations of the chip and can be discounted during the analysis process. The present invention discloses a method and apparatus used to avoid analyzing non-important paths, referred to as false paths of a directed timing graph. To avoid the false paths, the timing graph representing the circuit is modified to exclude the false paths before the graph is analyzed. To modify the timing graph, duplicate nodes are constructed, duplicate edges are constructed, and some edges of the original graph are cut and replaced by mixed edges connecting non-duplicate nodes to duplicate nodes. Finally, mixed edges are created to connect duplicate nodes to non-duplicate nodes, integrating the duplicate graph with the original graph.
摘要翻译： 集成电路芯片（IC）需要适当放置许多单元（电路组件组）和复杂的导线布线以连接单元的引脚。 IC的设计需要满足实际的限制，例如最小化电路面积，最小化电路内的电线长度，以及使IC执行其功能所需的时间最小化，称为IC延迟。 为了设计电路以满足给定的一组要求，必须分析电路的每个信号路径。 由于大量的单元和复杂的连接，路径数量非常多，需要很多计算能力进行分析。 此外，一些路径对于芯片的操作的目的不重要，并且可以在分析过程期间被折扣。 本发明公开了一种用于避免分析非重要路径的方法和装置，被称为定向定时图的假路径。 为了避免错误路径，修改表示电路的时序图，以排除图表分析之前的虚假路径。 为了修改时序图，构造了重复的节点，构建了重复的边，原始图的一些边被剪切，并将不重复的节点连接到重复节点的混合边替换。 最后，创建混合边以将重复节点连接到非重复节点，将重复图与原始图集成。
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公开(公告)号：US6068662A
公开(公告)日：2000-05-30
申请号：US906945
申请日：1997-08-06
CPC分类号： G06F17/5072
摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that placement of the cell and the wire routine be done correctly to avoid any congestion of wires. The present invention discloses method and apparatus to reduce or to eliminate cell placement and wire routing congestion. The congestion reduction is achieved by first examining regions of the IC to determine whether horizontal or vertical congestion exists. If horizontal congestion exists, then the cells are moved, within the columns, vertically to give more room for the cells and in between the cells for the routing of the wires. If vertical congestion exists, then the cells are moved to different columns to alleviate congestion. The present invention discloses techniques of determining horizontal and vertical congestion and the techniques for moving the cells. The movement of the cells to other columns may create overlapping of the cells or overloading of the columns. The present invention also discloses the methods to resolve the overlapping and overloading problems.
摘要翻译： 集成电路芯片（IC）需要适当放置许多单元（电路组件组）和复杂的导线布线以连接单元的引脚。 由于需要大量的单元和复杂的连接，所以必须正确地进行单元和电线程序的布置，以避免导线堵塞。 本发明公开了减少或消除小区布置和布线拥塞的方法和装置。 通过首先检查IC的区域以确定是否存在水平或垂直拥塞来实现拥塞减少。 如果存在水平拥堵，那么单元在列内垂直移动，为单元格提供更多的空间，并且在单元之间用于导线的布线。 如果存在垂直拥塞，则将小区移动到不同的列以减轻拥塞。 本发明公开了确定水平和垂直拥塞的技术以及移动小区的技术。 细胞到其他柱的运动可能造成细胞重叠或柱的重载。 本发明还公开了解决重叠和重载问题的方法。
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公开(公告)号：US6067409A
公开(公告)日：2000-05-23
申请号：US798598
申请日：1997-02-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A system for determining an affinity associated with relocating a cell located on a surface of a semiconductor chip to a different location on the surface is disclosed herein. Each cell may be part of a cell net containing multiple cells. The system initially defines a bounding box containing all cells in the net which contains the cell. The system then establishes a penalty vector based on the bounding box and borders of a region containing the cell, computes a normalized sum of penalties for all nets having the cell as a member, and calculates the affinity based on the normalized sum of penalties. Also included in the disclosed system are methods and apparatus for capacity and utilization planning of the use of the floor, or the surface area, and the methods and apparatus for parallelizing the process of affinity based placements using multiple processors. Finally, method and apparatus for connecting the cells based on a Steiner Tree method is disclosed.
摘要翻译： 本文公开了一种用于确定与将位于半导体芯片的表面上的单元重新定位到表面上的不同位置的亲和度的系统。 每个细胞可以是包含多个细胞的细胞网的一部分。 系统最初定义了包含网络中包含单元格的所有单元格的边界框。 然后，该系统基于边界框和包含单元格的区域的边界来建立惩罚向量，计算具有该单元作为成员的所有网络的归一化惩罚总和，并且基于标准化的惩罚总和来计算亲和度。 所公开的系统中还包括用于使用楼层或表面积的容量和利用规划的方法和装置，以及用于使用多个处理器并行化基于亲和力的布置的过程的方法和装置。 最后，公开了基于Steiner Tree方法连接单元的方法和装置。
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">6.发明授权Physical design automation system and process for designing integrated circuit chip using simulated annealing with "chessboard and jiggle" optimization 失效物理设计自动化系统和使用模拟退火设计集成电路芯片的过程用“棋盘和摆动”优化
公开(公告)号：US5796625A
公开(公告)日：1998-08-18
申请号：US609359
申请日：1996-03-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A cell placement for an integrated circuit chip is divided into two "chessboard" patterns or "jiggles". Each pattern resembles a chessboard in that it consists of alternating regions of different types or "colors" such that no region of a given color has an edge common with another region of the same color. The jiggles are offset relative to each other such that the regions of one jiggle partially overlap at least two regions of the other jiggle. Simulated annealing is performed sequentially for each color of each jiggle. During each operation, a plurality of parallel processors operate on the regions simultaneously using a previous copy of the entire chip, with one processor being assigned to one or more regions. At the end of each operation, the copy of the chip is updated. The chessboard patterns eliminate unproductive cell moves resulting from adjacent regions having a common edge. The jiggles enable cells to move to their optimal positions from their initial region to any other region on the chip. The regions can have rectangular, triangular or hexagonal shapes. An initial temperature for the actual simulated annealing operation is determined by performing simulated annealing without cell swaps with different temperature, and selecting the temperature at which a cost function such as total wirelength does not significantly change.
摘要翻译： 集成电路芯片的单元布局分为两个“棋盘”图案或“跳棋”。 每个图案类似于棋盘，其由不同类型或“颜色”的交替区域组成，使得给定颜色的区域不具有与相同颜色的另一区域相同的边缘。 跳块相对于彼此偏移，使得一个颤动的区域部分地与另一个摇摆的至少两个区域重叠。 对每个抖动的每个颜色依次执行模拟退火。 在每个操作期间，多个并行处理器使用整个芯片的先前副本同时在该区域上操作，一个处理器被分配给一个或多个区域。 在每个操作结束时，更新芯片的副本。 棋盘图案消除由具有共同边缘的相邻区域产生的非生产性细胞移动。 这些跳跃使得电池从它们的初始区域移动到其最佳位置到芯片上的任何其它区域。 这些区域可以具有矩形，三角形或六边形形状。 实际模拟退火操作的初始温度是通过进行模拟退火而不使用不同温度的电池互换来确定的，并且选择诸如总线长度的成本函数不会显着改变的温度。
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公开(公告)号：US07194717B2
公开(公告)日：2007-03-20
申请号：US10936202
申请日：2004-09-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G11C5/02 , G11C5/04
摘要： The present invention provides a layout method for a top module including instances of a base module in a memory matrix such as a RRAM memory matrix, and the like. The top module and the base module may each include data pins and at least one control pin, or the top module and the base module may each include data pins only and may not include any control pins. The data pins of the instances of the base module are replicated in the top module. When at least one control pin is included in the top module and the base module, a control signal may be shared among the instances of the base module and the top module by tying together corresponding control pins of the instances and a corresponding control pin of the top module. The present method may include steps as follows. At a library preparation stage, data pins (and control pins, if applicable) of standard cells in the top module are extended vertically for easy access. Then, positions for the data pins of the top module (and at least one control pin, if applicable) of the top module are assigned in the top module. The instances are arranged within the top module. Signal routing for the instances and the top module are implemented. Power routing is performed for the instances and the top module.
摘要翻译： 本发明提供一种包括诸如RRAM存储矩阵等存储矩阵中的基本模块的实例的顶部模块的布局方法。 顶部模块和基本模块可以各自包括数据引脚和至少一个控制引脚，或者顶部模块和基本模块可以各自包括数据引脚，并且可以不包括任何控制引脚。 基本模块的实例的数据引脚在顶部模块中复制。 当至少一个控制引脚被包括在顶部模块和基本模块中时，控制信号可以通过将实例的对应的控制引脚和相应的控制引脚相连接在一起，在基本模块和顶部模块的实例之间共享 顶部模块。 本方法可以包括以下步骤。 在图书馆准备阶段，顶部模块中的标准单元的数据引脚（和控制引脚（如果适用））垂直延伸以方便访问。 然后，顶部模块的顶部模块（和至少一个控制引脚（如果适用））的数据引脚的位置被分配在顶部模块中。 实例被布置在顶部模块内。 实现实例和顶层模块的信号路由。 为实例和顶部模块执行电源路由。
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公开(公告)号：US06760896B2
公开(公告)日：2004-07-06
申请号：US10254607
申请日：2002-09-25
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： A bus is defined on a core of an integrated circuit. Routing lines are defined through the core, and net wires are routed through the core along respective routing lines. Buffer columns are defined in the core across a plurality of nets, and buffers are placed in the buffer columns so that an input and output to a respective buffer are on different routing lines. The buffers have at least one free routing line and the net wires are redistribution across the buffer so that (i) the net wire to be buffered is re-routed to the input and output of the buffer, (ii) the net wires on routing lines containing the input and output of the buffer are re-routed to the routing line of the net wire to be buffered and the free routing line, and (iii) all other net wires are routed along their respective routing lines.
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公开(公告)号：US06186676B1
公开(公告)日：2001-02-13
申请号：US08906947
申请日：1997-08-06
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that wire routine be done correctly to avoid any congestion of wires. Congestion of wires can be determined by actually routing of the wires to connect the cells; however, the routing process is computationally expensive. For determination of congestion, the only required information are the location of the connections, or edges, to connect the pins of the IC. The present invention discloses a method to quickly provide a good estimate of the location of the edges, or connections for an IC. The present invention provides for a method to determine all the edges and superedges (bounding boxes, or areas where an edge will take space) of an IC without requiring to determine the actual routing of the wires of an IC.
摘要翻译： 集成电路芯片（IC）需要适当放置许多单元（电路组件组）和复杂的导线布线以连接单元的引脚。 由于需要大量的单元和复杂的连接，因此必须正确地进行线路程序，以避免导线的拥塞。 可以通过实际布线连接电池来确定电线的拥塞; 然而，路由过程在计算上是昂贵的。 为了确定拥塞，唯一需要的信息是连接IC的引脚的连接或边缘的位置。 本发明公开了一种快速提供对于IC的边缘或连接的位置的良好估计的方法。 本发明提供了一种确定集成电路的所有边缘和覆盖（边界将占据空间的区域）的方法，而不需要确定IC的导线的实际布线。
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公开(公告)号：US6123736A
公开(公告)日：2000-09-26
申请号：US906949
申请日：1997-08-06
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that placement of the cell and the wire routine be done correctly to avoid any congestion of wires. Placement of the cells and the routing of the wires to avoid congestion can be accomplished by determining congestion of various regions, or pieces, of the IC's after an initial placement of the cells and routing of the wires. The present invention discloses a method and apparatus to define the regions, or pieces, of the IC, determine various density measurement of the pieces, and adjust the sizes of the pieces to reduce congestion of congested pieces by reallocating space from uncongested pieces to congested pieces. In addition, the present invention discloses the technique of adjusting the sizes of the piece to minimize disturbing the placement and wire routing while the congestion is being reduced. This is accomplished by comparing the vertical location of each of the pieces to the vertical location of the pieces next to it.
摘要翻译： 集成电路芯片（IC）需要适当放置许多单元（电路组件组）和复杂的导线布线以连接单元的引脚。 由于需要大量的单元和复杂的连接，所以必须正确地进行单元和电线程序的布置，以避免导线堵塞。 可以通过在单元的初始放置和导线的布线之后确定IC的各个区域或多个块的拥塞来实现单元的放置和布线以避免拥塞。 本发明公开了一种用于限定IC的区域或片段的方法和装置，确定片段的各种密度测量，并调整片段的尺寸，以通过将空隙重新分配成未充塞的片段到拥塞的部分来减少拥塞片的拥塞 。 此外，本发明公开了一种在减少拥塞的情况下调整片的大小以最小化扰乱布局和布线的技术。 这是通过将每个片段的垂直位置与其旁边的片段的垂直位置进行比较来实现的。
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