公开(公告)号：US20110082961A1

公开(公告)日：2011-04-07

申请号：US12892862

申请日：2010-09-28

申请人： Alexander L. Minkin ,  Steven L. Heinrich ,  Rajeshwaran Selvanesan ,  Stewart Glenn Carlton ,  John R. Nickolls

发明人： Alexander L. Minkin ,  Steven L. Heinrich ,  Rajeshwaran Selvanesan ,  Stewart Glenn Carlton ,  John R. Nickolls

IPC分类号： G06F13/36 ,  G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/4031

摘要： The invention sets forth an L1 cache architecture that includes a crossbar unit configured to transmit data associated with both read data requests and write data requests. Data associated with read data requests is retrieved from a cache memory and transmitted to the client subsystems. Similarly, data associated with write data requests is transmitted from the client subsystems to the cache memory. To allow for the transmission of both read and write data on the crossbar unit, an arbiter is configured to schedule the crossbar unit transmissions as well and arbitrate between data requests received from the client subsystems.

摘要翻译： 本发明提出了一种L1缓存架构，其包括被配置为发送与读取数据请求和写入数据请求相关联的数据的交叉单元。 与读取数据请求相关联的数据从高速缓冲存储器检索并发送到客户机子系统。 类似地，与写数据请求相关联的数据从客户端子系统发送到高速缓冲存储器。 为了允许在交叉开关单元上传输读取和写入数据，仲裁器被配置为调度交叉单元传输以及在从客户端子系统接收的数据请求之间进行仲裁。