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    INTERCONNECTING RECONFIGURABLE REGIONS IN A FIELD PROGRAMMABLE GATE ARRAY
    2.
    发明公开
    INTERCONNECTING RECONFIGURABLE REGIONS IN A FIELD PROGRAMMABLE GATE ARRAY 审中-公开

    公开(公告)号：US20240354271A1

    公开(公告)日：2024-10-24

    申请号：US18682420

    申请日：2022-08-04

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： Ahsan Javed AWAN ,  Fidan ALIYEVA

    IPC分类号： G06F13/40

    CPC分类号： G06F13/4022

    摘要： The present disclosure provides a Field Programmable Gate Array (FPGA). The FPGA comprises a plurality of regions, each of the regions being reconfigurable independently of one another. The FPGA further comprises a crossbar switch connected to the plurality of regions, wherein the crossbar switch is configurable to connect at least one first region in the plurality of regions to at least one second region in the plurality of regions such that the at least one first region is operable to communicate with the at least one second region.

    Techniques for release assistance indication assertion
    6.
    发明授权
    Techniques for release assistance indication assertion 有权

    公开(公告)号：US12118878B2

    公开(公告)日：2024-10-15

    申请号：US18503924

    申请日：2023-11-07

    申请人： ITRON, INC.

    发明人： Richard Donald Maes, II ,  Robert Vernon Dusenberry ,  Eric S. Benson

    IPC分类号： G08C17/02 ,  G06F13/38 ,  G06F13/40

    CPC分类号： G08C17/02 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4059 ,  G08C2201/42

    摘要： Techniques for transmitting data include one or more processors of a computing device included in a network device identifying data to be transmitted; and while a data session window is open: transmitting, using a transmitter of the network device, the data to a transceiver that is included in the network device and is separate from the one or more processors, wherein the transceiver is configured to transmit the data outside of the network device; and in response to determining that there is no additional data to be transmitted, (a) delaying for a period of time, and (b) after the period of time, instructing the transceiver to end the data session window early and transition to a lower power state.

    Multi-path server and multi-path server signal interconnection system
    7.
    发明授权
    Multi-path server and multi-path server signal interconnection system 有权

    公开(公告)号：US12117952B2

    公开(公告)日：2024-10-15

    申请号：US18276413

    申请日：2021-09-28

    申请人： Shandong Yingxin Computer Technologies Co., Ltd.

    发明人： Xiangtao Kong

    IPC分类号： G06F13/40

    CPC分类号： G06F13/4022

    摘要： The multi-path server comprises four circuits. Each circuit comprises a PCH, an extended module, a switch module, and a CPU. An extended module in the first circuit is connected to a switch module in the second circuit, a switch module in the third circuit, and a switch module in the fourth circuit. An extended module in the third circuit is connected to a switch module in the fourth circuit. A switch module performs switching action according to a target partition instruction, and a PCH performs in-place action according to the target partition instruction, such that each said circuit forms a target partition, and PMSYNC signals are interconnected in the target partition. A multi-path server signal interconnection system is also provided.

    NoC buffer management for virtual channels
    10.
    发明授权
    NoC buffer management for virtual channels 有权

    公开(公告)号：US12111784B2

    公开(公告)日：2024-10-08

    申请号：US17959903

    申请日：2022-10-04

    申请人： XILINX, INC.

    发明人： Krishnan Srinivasan ,  Abbas Morshed ,  Sagheer Ahmad

    IPC分类号： G06F13/40

    CPC分类号： G06F13/4059 ,  G06F13/4022

    摘要： Embodiments herein describe a NoC where its internal switches have buffers with pods that can be assigned to different virtual channels. A subset of the pods in a buffer can be grouped together to form a VC. In this manner, different pod groups in a buffer can be assigned to different VCs (or to different types of NoC data units), where VCs that transmit wider data units can be assigned more pods than VCs that transmit narrower data units.