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公开(公告)号：US20130107957A1
公开(公告)日：2013-05-02
申请号：US13285353
申请日：2011-10-31
IPC分类号： H04N7/32
CPC分类号： H04N19/11 , H04N19/147 , H04N19/176 , H04N19/423 , H04N19/593
摘要： An apparatus having a memory and a circuit is disclosed. The memory may be configured to store a picture being encoded. The circuit may be configured to calculate a plurality of first arrays directly from a plurality of neighboring samples around a current block of the picture. Each first array generally represents a respective one of a plurality of intra-prediction modes. Each first array may be spatially smaller than the current block. The circuit may also be configured to calculate a second array from a plurality of current samples in the current block. The second array may spatially match the first arrays. The circuit may be further configured to generate a plurality of scores of the intra-prediction modes by comparing the first arrays with the second array and select a given one of the intra-prediction modes corresponding to a lowest of the scores to encode the current block.
摘要翻译： 公开了一种具有存储器和电路的装置。 存储器可以被配置为存储被编码的图像。 电路可以被配置为直接从图像的当前块周围的多个相邻样本计算多个第一阵列。 每个第一阵列通常表示多个帧内预测模式中的相应一个。 每个第一阵列可以在空间上小于当前块。 电路还可以被配置为从当前块中的多个当前样本计算第二阵列。 第二阵列可以在空间上匹配第一阵列。 该电路还可以被配置为通过将第一阵列与第二阵列进行比较来产生多个分数的帧内预测模式，并且选择与最低分数相对应的帧内预测模式中的给定一个来编码当前块 。
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公开(公告)号：US20130136181A1
公开(公告)日：2013-05-30
申请号：US13307393
申请日：2011-11-30
IPC分类号： H04N7/32
CPC分类号： H04N19/533 , H04N19/433
摘要： An apparatus having a cache and a processor. The cache may be configured to (i) buffer a first subset of reference samples of a reference picture to facilitate a motion estimation of a current block and (ii) prefetch a second subset of the reference samples while a first search pattern is being tested. The first search pattern used in the motion estimation generally defines multiple motion vectors to test. The reference samples of the second subset may be utilized by a second search pattern in the motion estimation of the current block. The prefetch of the second subset may be based on a geometry of the first search pattern and scores of the motion vectors already tested. The processor may be configured to calculate the scores of the motion vectors by a block comparison of the reference samples to the current block according to the first search pattern.
摘要翻译： 具有高速缓存和处理器的装置。 高速缓存可以被配置为（i）缓冲参考图片的参考样本的第一子集，以促进当前块的运动估计，以及（ii）在测试第一搜索模式的同时预取参考样本的第二子集。 在运动估计中使用的第一搜索模式通常定义要测试的多个运动矢量。 第二子集的参考样本可以由当前块的运动估计中的第二搜索模式来利用。 第二子集的预取可以基于第一搜索模式的几何形状和已经测试的运动矢量的分数。 处理器可以被配置为根据第一搜索模式通过参考样本与当前块的块比较来计算运动矢量的得分。
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3.发明申请Direct Memory Access With On-The-Fly Generation of Frame Information For Unrestricted Motion Vectors 审中-公开直接存储器访问，用于不受限制的运动矢量的帧信息的即时生成公开(公告)号：US20130094586A1
公开(公告)日：2013-04-18
申请号：US13274422
申请日：2011-10-17
IPC分类号： H04N7/32
CPC分类号： H04N19/427
摘要： A method for performing motion estimation based on at least a first VOP stored in a memory includes the steps of: receiving a request to read a data block indicative of at least a portion of the first VOP for predicting a second VOP that is temporally adjacent to the first VOP; utilizing a DMA module for determining whether the data block is a UMV block; translating a block address for retrieving at least a portion of the data block from the memory as a function of one or more parameters generated by the DMA module; and generating a complete data block as a function of the portion of the data block retrieved from the memory and the one or more parameters generated by the DMA module.
摘要翻译： 一种用于基于存储在存储器中的至少第一VOP执行运动估计的方法包括以下步骤：接收读取指示第一VOP的至少一部分的数据块的请求，用于预测与时间上相邻的第二VOP 第一个VOP; 利用DMA模块来确定数据块是否是UMV块; 根据由所述DMA模块生成的一个或多个参数来转换用于从所述存储器检索所述数据块的至少一部分的块地址; 以及根据从存储器检索的数据块的部分和由DMA模块生成的一个或多个参数，生成完整的数据块。
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公开(公告)号：US20130080741A1
公开(公告)日：2013-03-28
申请号：US13246184
申请日：2011-09-27
CPC分类号： G06F9/325 , G06F9/3867 , G06F9/3877
摘要： An apparatus generally having a first circuit, a second circuit and a third circuit is disclosed. The first circuit may have a counter and may be configured to adjust at least one control signal in response to a current value of the counter. The first circuit may be implemented only in hardware. The counter generally counts a number of loops in which a plurality of instructions are executed. The second circuit may be configured to set the counter to an initial value. The third circuit may be configured to execute the instructions using a plurality of data items as a plurality of operands such that at least two of the instructions use different ones of the operands. The data items may be routed to the third circuit in response to the control signal. The apparatus generally forms a processor.
摘要翻译： 公开了一种通常具有第一电路，第二电路和第三电路的装置。 第一电路可以具有计数器并且可以被配置为响应于计数器的当前值来调整至少一个控制信号。 第一电路可以仅在硬件中实现。 该计数器通常对执行多个指令的循环进行计数。 第二电路可以被配置为将计数器设置为初始值。 第三电路可以被配置为使用多个数据项作为多个操作数来执行指令，使得至少两个指令使用不同的操作数。 数据项可以响应于控制信号被路由到第三电路。 该装置通常形成处理器。
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公开(公告)号：US20130298129A1
公开(公告)日：2013-11-07
申请号：US13465179
申请日：2012-05-07
IPC分类号： G06F9/46
CPC分类号： G06F9/3836 , G06F9/381 , G06F9/3885
摘要： An apparatus having a first circuit and a plurality of second circuits is disclosed. The first circuit may be configured to dispatch a plurality of sets in a sequence. Each set generally includes a plurality of instructions. The second circuits may be configured to (i) execute the sets during a plurality of execution cycles respectively and (ii) stop the execution in a particular one of the second circuits during one or more of the execution cycles in response to an expiration of a particular counter that corresponds to the particular second circuit.
摘要翻译： 公开了一种具有第一电路和多个第二电路的装置。 第一电路可以被配置为按顺序调度多个集合。 每个集合通常包括多个指令。 第二电路可以被配置为：（i）分别在多个执行周期期间执行集合，以及（ii）在一个或多个执行周期期间响应于一个或多个执行周期的期满而停止在特定的一个第二电路中的执行 对应于特定第二电路的特定计数器。
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公开(公告)号：US08527689B2
公开(公告)日：2013-09-03
申请号：US12914070
申请日：2010-10-28
CPC分类号： G09G5/399 , G06F13/28 , G09G2320/0261 , G09G2360/127 , G09G2360/18 , G09G2370/12 , Y02D10/14
摘要： An apparatus generally including an internal memory and a direct memory access controller is disclosed. The direct memory access controller may be configured to (i) read first information from an external memory across an external bus, (ii) generate second information by processing the first information, (iii) write the first information across an internal bus to a first location in the internal memory during a direct memory access transfer and (iv) write the second information across the internal bus to a second location in the internal memory during the direct memory access transfer. The second location may be different from the first location.
摘要翻译： 公开了一种通常包括内部存储器和直接存储器存取控制器的装置。 直接存储器访问控制器可以被配置为：（i）通过外部总线从外部存储器读取第一信息，（ii）通过处理第一信息生成第二信息，（iii）将第一信息跨内部总线写入第一信息 在直接存储器访问转移期间内部存储器中的位置和（iv）在直接存储器访问传输期间将第二信息跨内部总线写入内部存储器中的第二位置。 第二位置可以不同于第一位置。
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公开(公告)号：US20130208796A1
公开(公告)日：2013-08-15
申请号：US13396904
申请日：2012-02-15
CPC分类号： H04N19/53 , H04N19/433 , H04N19/61
摘要： An apparatus having a cache and a processor is disclosed. The cache may be configured to (i) buffer a first subset of a reference picture to facilitate a motion estimation of a current block at a first level of a hierarchical motion estimation and (ii) prefetch a second subset of the reference picture to the cache in response to an occurrence of a condition before the motion estimation is completed at the first level. The processor may be configured to calculate a plurality of scores by comparing the current block with the first subset of the reference picture. The second subset generally (i) resides at a second level of the hierarchical motion estimation and (ii) may be determined from the scores calculated prior to the occurrence of the condition.
摘要翻译： 公开了一种具有高速缓存和处理器的设备。 高速缓存可以被配置为（i）缓冲参考图片的第一子集，以促进在分层运动估计的第一级别处的当前块的运动估计，以及（ii）将参考图片的第二子集预取到高速缓存 响应于在第一级完成运动估计之前的状况的发生。 处理器可以被配置为通过将当前块与参考图片的第一子集进行比较来计算多个分数。 第二子集通常（i）位于层次运动估计的第二级，并且（ii）可以根据条件发生之前计算的分数来确定。
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公开(公告)号：US20130113543A1
公开(公告)日：2013-05-09
申请号：US13292377
申请日：2011-11-09
IPC分类号： G06G7/16
CPC分类号： G06F7/53 , G06F7/4991
摘要： An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) receive two input signals. Each input signal generally carries a respective data value. Each data value may have a respective sign bit and a respective at least one guard bit. The first circuit may also be configured to (ii) scale each data value independently such that all of the respective guard bits have a same value as the respective sign bit and (iii) generate a product value in an output signal by adjusting an intermediate value based on the scaling of the data values. The second circuit may be configured to generate the intermediate value by multiplying the two data values as scaled.
摘要翻译： 公开了一种具有第一电路和第二电路的装置。 第一电路可以被配置为（i）接收两个输入信号。 每个输入信号通常携带相应的数据值。 每个数据值可以具有相应的符号位和相应的至少一个保护位。 第一电路还可以被配置为（ii）独立地缩放每个数据值，使得所有相应的保护位具有与相应符号位相同的值，以及（iii）通过调整中间值来产生输出信号中的乘积值 基于数据值的缩放。 第二电路可以被配置为通过将两个数据值乘以比例来生成中间值。
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9.发明申请公开(公告)号：US20130094567A1
公开(公告)日：2013-04-18
申请号：US13275715
申请日：2011-10-18
CPC分类号： H04N19/433 , G09G5/39 , G09G2320/106 , G09G2340/02 , G09G2360/122 , H04N19/51 , H04N19/61
摘要： A data processing system for processing a video stream comprises memory array circuitry, memory access circuitry, and video processing circuitry. The memory array circuitry is characterized by a width and a height. The memory access circuitry is operative to cause, through a series of write operations, a series of two-dimensional data representations of different respective regions in a frame of the video stream to be stored in the memory array circuitry. The write operations occur such that only data missing from the memory array circuitry is written to the memory array circuitry during each write operation and such that the data is written modulo at least one of the width and the height of the memory array circuitry. Lastly, the video processing circuitry is operative to perform block matching on the video stream at least in part utilizing the series of two-dimensional data representations stored in the memory array circuitry.
摘要翻译： 用于处理视频流的数据处理系统包括存储器阵列电路，存储器存取电路和视频处理电路。 存储器阵列电路的特征在于宽度和高度。 存储器访问电路可操作以通过一系列写入操作使得要存储在存储器阵列电路中的视频流的帧中的不同相应区域的一系列二维数据表示。 写入操作发生，使得仅在存储器阵列电路中丢失的数据在每个写入操作期间被写入存储器阵列电路，并且使得数据被写入存储器阵列电路的宽度和高度中的至少一个。 最后，视频处理电路用于至少部分利用存储在存储器阵列电路中的一系列二维数据表示来对视频流执行块匹配。
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公开(公告)号：US20120110232A1
公开(公告)日：2012-05-03
申请号：US12914070
申请日：2010-10-28
IPC分类号： G06F13/28
CPC分类号： G09G5/399 , G06F13/28 , G09G2320/0261 , G09G2360/127 , G09G2360/18 , G09G2370/12 , Y02D10/14
摘要： An apparatus generally including an internal memory and a direct memory access controller is disclosed. The direct memory access controller may be configured to (i) read first information from an external memory across an external bus, (ii) generate second information by processing the first information, (iii) write the first information across an internal bus to a first location in the internal memory during a direct memory access transfer and (iv) write the second information across the internal bus to a second location in the internal memory during the direct memory access transfer. The second location may be different from the first location.
摘要翻译： 公开了一种通常包括内部存储器和直接存储器存取控制器的装置。 直接存储器访问控制器可以被配置为：（i）通过外部总线从外部存储器读取第一信息，（ii）通过处理第一信息生成第二信息，（iii）将第一信息跨内部总线写入第一信息 在直接存储器访问转移期间内部存储器中的位置和（iv）在直接存储器访问传输期间将第二信息跨内部总线写入内部存储器中的第二位置。 第二位置可以不同于第一位置。
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