公开(公告)号：US11722141B1

公开(公告)日：2023-08-08

申请号：US17660221

申请日：2022-04-22

Applicant: Allegro MicroSystems, LLC

Inventor： Leo Filippini ,  Charles Myers ,  Adam Lee

IPC: H03L7/095 ,  H03L7/081

CPC classification number: H03L7/095 ,  H03L7/0812

Abstract: Systems, methods, and circuits provide delay-locked loop (DLL) timing error mitigation. A DLL false-lock detection system can include DLL circuitry configured to receive a reference clock signal having a time period. The system can include shift register circuitry and latched comparison circuitry which can determine a time period of a locked condition of the DLL delay line with respect to the reference clock signal time period. The system can determine whether the system is correctly locked to the base time period or incorrectly locked to a multiple of the base time period. A further system can operate to cause a phase detector circuitry in a DLL to ignore the first edge of a reference clock signal presented to the phase detector circuitry and thereby avoid stuck-lock conditions.