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1.发明授权公开(公告)号：US11327882B2
公开(公告)日：2022-05-10
申请号：US16782139
申请日：2020-02-05
Applicant: Allegro MicroSystems, LLC
Inventor： Muhammed Sarwar , Vyankatesh Gupta , James McClay , Sundar Chetlur , Harianto Wong , Gerardo A. Monreal , Nicolás Rafael Biberidis , Octavio H. Alpago , Nicolas Rigoni
Abstract: A method comprising: performing a first read from an address in a data storage module by using a first read voltage; storing, in a first register, data that is retrieved from the data storage module as a result of the first read; performing a second read from the address by using a second read voltage; storing, in a second register, data that is retrieved from the data storage module as a result of the second read; detecting whether a weak bit condition is present at the address based on the data that is stored in the first register and the data that is stored in the second register; and correcting the weak bit condition, when the weak bit condition is present at the address.
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2.发明申请公开(公告)号：US20210240606A1
公开(公告)日：2021-08-05
申请号：US16782139
申请日：2020-02-05
Applicant: Allegro MicroSystems, LLC
Inventor： Muhammed Sarwar , Vyankatesh Gupta , James McClay , Sundar Chetlur , Harianto Wong , Gerardo A. Monreal , Nicolás Rafael Biberidis , Octavio H. Alpago , Nicolas Rigoni
Abstract: A method comprising: performing a first read from an address in a data storage module by using a first read voltage; storing, in a first register, data that is retrieved from the data storage module as a result of the first read; performing a second read from the address by using a second read voltage; storing, in a second register, data that is retrieved from the data storage module as a result of the second read; detecting whether a weak bit condition is present at the address based on the data that is stored in the first register and the data that is stored in the second register; and correcting the weak bit condition, when the weak bit condition is present at the address.
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