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    CIRCUITS HAVING ENHANCED ELECTRICAL ISOLATION
    1.
    发明公开
    CIRCUITS HAVING ENHANCED ELECTRICAL ISOLATION 审中-公开

    公开(公告)号：US20240120371A1

    公开(公告)日：2024-04-11

    申请号：US18045528

    申请日：2022-10-11

    Applicant: Allegro MicroSystems, LLC

    Inventor： James McClay ,  Maxim Klebanov ,  Sundar Chetlur ,  Thomas S. Chung

    IPC: H01L29/06 ,  H01L27/11524 ,  H01L29/788

    CPC classification number: H01L29/0646 ,  H01L27/11524 ,  H01L29/7883

    Abstract: Methods and apparatus for a device that includes a circuit, such as a memory cell, and an isolation structure to electrically isolate the circuit cell. The isolation structure can include a p-type substrate, a first series of p-type material extending to the p-type substrate, and a second series of p-type material extending to the p-type substrate. The first series of p-type material, the p-type substrate, and the second series of p-type material surrounds a first side, a second side, and a bottom of the circuit cell to electrically isolate the circuit cell with continuous p-type material. In some embodiments, the first series of p-type material comprises p-type well regions. In some embodiments, the first series of p-type material comprises deep trench isolation.

    ELECTROSTATIC DISCHARGE PROTECTION DEVICE INCLUDING PARASITIC MOSFET FORMED USING TRENCH
    3.
    发明公开
    ELECTROSTATIC DISCHARGE PROTECTION DEVICE INCLUDING PARASITIC MOSFET FORMED USING TRENCH 审中-公开

    公开(公告)号：US20240170478A1

    公开(公告)日：2024-05-23

    申请号：US18058318

    申请日：2022-11-23

    Applicant: Allegro MicroSystems, LLC

    Inventor： Chung C. Kuo ,  Maxim Klebanov ,  James McClay ,  Sagar Saxena

    IPC: H01L27/02

    CPC classification number: H01L27/0274

    Abstract: In one aspect, a semiconductor device includes a first region, a second region and a trench separating the first and the second regions. The trench includes a trench liner that includes a dielectric, and a semiconductor material surrounded by the trench liner. The first region includes a first buried layer implanted in a substrate, a first stack of layers that includes a first middle layer located above the first buried layer, a first well located on and in contact with the first middle layer and a second well in contact with the first well. The second region includes a second stack of layers. In response to a voltage difference between the first and the second regions exceeding a threshold voltage, a conduction current is formed. A distance of the first stack of layers to the trench controls the conduction current to activate a transistor to function as a voltage clamp.

    Method of multiple gate oxide forming with hard mask
    8.
    发明授权
    Method of multiple gate oxide forming with hard mask 有权

    公开(公告)号：US10916438B2

    公开(公告)日：2021-02-09

    申请号：US16407500

    申请日：2019-05-09

    Applicant: Allegro MicroSystems, LLC

    Inventor： Maxim Klebanov ,  Sundar Chetlur ,  James McClay

    IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/336 ,  H01L21/308 ,  H01L21/033 ,  H01L29/51

    Abstract: Methods for fabricating an integrated circuit having a plurality of gate dielectrics. The methods are provided to include: forming one or more isolation trenches and a first active region and a second active region in a substrate; depositing hard mask material on the substrate; removing a first portion of the hard mask material over the first active region; forming a first oxide layer having a first thickness over the first active region; removing a second portion of the hard mask material over the second active region; and forming a second oxide layer having a second thickness over the first and second active regions such that a thickness of oxide formed over the first active region comprises a sum of the thickness of the first oxide layer and the second oxide layer, and a thickness of oxide formed over the second active region comprises the second thickness.

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