公开(公告)号：US12260317B1

公开(公告)日：2025-03-25

申请号：US16525460

申请日：2019-07-29

Applicant: Amazon Technologies, Inc.

Inventor： Brian Thomas ,  Steven L. Teig

IPC: G06N3/063 ,  G06F17/16 ,  G06N3/04

Abstract: Some embodiments provide a compiler for optimizing the implementation of a machine-trained network (e.g., a neural network) on an integrated circuit (IC). The compiler of some embodiments receives a specification of a machine-trained network including multiple layers of computation nodes and generates a graph representing options for implementing the machine-trained network in the IC. In some embodiments, the compiler also generates instructions for gating operations. Gating operations, in some embodiments, include gating at multiple levels (e.g., gating of clusters, cores, or memory units). Gating operations conserve power in some embodiments by gating signals so that they do not reach the gated element or so that they are not propagated within the gated element. In some embodiments, a clock signal is gated such that a register that transmits data on a rising (or falling) edge of a clock signal is not triggered.