公开(公告)号：US12299555B2

公开(公告)日：2025-05-13

申请号：US17894798

申请日：2022-08-24

Applicant: Amazon Technologies, Inc.

Inventor： Steven L. Teig ,  Eric A. Sather

IPC: G06N3/04 ,  G06F17/12 ,  G06F17/18 ,  G06F18/211 ,  G06N3/08 ,  G06N3/084 ,  G06N20/00

Abstract: Some embodiments provide an electronic device that includes a set of processing units and a set of machine-readable media. The set of machine-readable media stores sets of instructions for applying a network of computation nodes to an input received by the device. The set of machine-readable media stores at least two sets of machine-trained parameters for configuring the network for different types of inputs. A first of the sets of parameters is used for applying the network to a first type of input and a second of the sets of parameters is used for applying the network to a second type of input.

公开(公告)号：US12260317B1

公开(公告)日：2025-03-25

申请号：US16525460

申请日：2019-07-29

Applicant: Amazon Technologies, Inc.

Inventor： Brian Thomas ,  Steven L. Teig

IPC: G06N3/063 ,  G06F17/16 ,  G06N3/04

Abstract: Some embodiments provide a compiler for optimizing the implementation of a machine-trained network (e.g., a neural network) on an integrated circuit (IC). The compiler of some embodiments receives a specification of a machine-trained network including multiple layers of computation nodes and generates a graph representing options for implementing the machine-trained network in the IC. In some embodiments, the compiler also generates instructions for gating operations. Gating operations, in some embodiments, include gating at multiple levels (e.g., gating of clusters, cores, or memory units). Gating operations conserve power in some embodiments by gating signals so that they do not reach the gated element or so that they are not propagated within the gated element. In some embodiments, a clock signal is gated such that a register that transmits data on a rising (or falling) edge of a clock signal is not triggered.

公开(公告)号：US20250103341A1

公开(公告)日：2025-03-27

申请号：US18824034

申请日：2024-09-04

Applicant: Amazon Technologies, Inc.

Inventor： Kenneth Duong ,  Jung Ko ,  Steven L. Teig

IPC: G06F9/38 ,  G06F15/80 ,  G06N3/063 ,  G06N5/046

Abstract: Some embodiments provide a neural network inference circuit (NNIC) for executing a neural network that includes multiple computation nodes at multiple layers. The NNIC includes multiple core circuits including memories for storing input values for the computation nodes. The NNIC includes a set of post-processing circuits for computing output values of the computation nodes. The output values for a first layer are for storage in the core circuits as input values for a second layer. The NNIC includes an output bus that connects the post-processing circuits to the core circuits. The output bus is for (i) receiving a set of output values from the post-processing circuits, (ii) transporting the output values of the set to the core circuits based on configuration data specifying a core circuit at which each of the output values is to be stored, and (iii) aligning the output values for storage in the core circuits.

公开(公告)号：US12299068B2

公开(公告)日：2025-05-13

申请号：US18384529

申请日：2023-10-27

Applicant: Amazon Technologies, Inc.

Inventor： Kenneth Duong ,  Jung Ko ,  Steven L. Teig

IPC: G06F17/16 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06T1/20 ,  G06V40/16

Abstract: Some embodiments provide an IC for implementing a machine-trained network with multiple layers. The IC includes a set of circuits to compute a dot product of (i) a first number of input values computed by other circuits of the IC and (ii) a set of predefined weight values, several of which are zero, with a weight value for each of the input values. The set of circuits includes (i) a dot product computation circuit to compute the dot product based on a second number of inputs and (ii) for each input value, at least two sets of wires for providing the input value to at least two of the dot product computation circuit inputs. The second number is less than the first number. Each input value with a corresponding weight value that is not equal to zero is provided to a different one of the dot product computation circuit inputs.

公开(公告)号：US20250148644A1

公开(公告)日：2025-05-08

申请号：US18737459

申请日：2024-06-07

Applicant: Amazon Technologies, Inc.

Inventor： Andrew C. Mihal ,  Steven L. Teig

IPC: G06T7/80 ,  G06N3/04 ,  G06N3/042 ,  G06N3/08 ,  G06N3/084 ,  G06T7/521 ,  G06T7/55 ,  G06T7/593 ,  G06V20/58 ,  G08G1/16 ,  H04N13/239 ,  H04N13/246

Abstract: Some embodiments of the invention provide a novel method for training a multi-layer node network. Some embodiments train the multi-layer network using a set of inputs generated with random misalignments incorporated into the training data set. In some embodiments, the training data set is a synthetically generated training set based on a three-dimensional ground truth model as it would be sensed by a sensor array from different positions and with different deviations from ideal alignment and placement. Some embodiments dynamically generate training data sets when a determination is made that more training is required. Training data sets, in some embodiments, are generated based on training data sets for which the multi-layer node network has produced bad results.

公开(公告)号：US12265905B2

公开(公告)日：2025-04-01

申请号：US17984228

申请日：2022-11-09

Applicant: Amazon Technologies, Inc.

Inventor： Jung Ko ,  Kenneth Duong ,  Steven L. Teig

IPC: G06F7/544 ,  G06F1/03 ,  G06F5/01 ,  G06F9/30 ,  G06F17/10 ,  G06F17/16 ,  G06N3/048 ,  G06N3/06 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084 ,  G06N5/04 ,  G06N5/046 ,  G06N20/00

Abstract: Some embodiments provide a method for a circuit that executes a neural network including multiple nodes. The method loads a set of weight values for a node into a set of weight value buffers, a first set of bits of each input value of a set of input values for the node into a first set of input value buffers, and a second set of bits of each of the input values into a second set of input value buffers. The method computes a first dot product of the weight values and the first set of bits of each input value and a second dot product of the weight values and the second set of bits of each input value. The method shifts the second dot product by a particular number of bits and adds the first dot product with the bit-shifted second dot product to compute a dot product for the node.

公开(公告)号：US12248880B2

公开(公告)日：2025-03-11

申请号：US18238507

申请日：2023-08-27

Applicant: Amazon Technologies, Inc.

Inventor： Eric A. Sather ,  Steven L. Teig ,  Andrew C. Mihal

IPC: G06N3/084 ,  G06F18/21 ,  G06F18/214 ,  G06N3/04 ,  G06N3/08 ,  G06T7/00 ,  G06V10/44 ,  G06V10/764 ,  G06V10/82 ,  G06V40/16

Abstract: Some embodiments provide a method for training a machine-trained (MT) network that processes inputs using network parameters. The method propagates a set of input training items through the MT network to generate a set of output values. The set of input training items comprises multiple training items for each of multiple categories. The method identifies multiple training item groupings in the set of input training items. Each grouping includes at least two training items in a first category and at least one training item in a second category. The method calculates a value of a loss function as a summation of individual loss functions for each of the identified training item groupings. The individual loss function for each particular training item grouping is based on the output values for the training items of the grouping. The method trains the network parameters using the calculated loss function value.