公开(公告)号：US11308026B1

公开(公告)日：2022-04-19

申请号：US16915777

申请日：2020-06-29

Applicant: Amazon Technologies, Inc.

Inventor： Thomas A Volpe ,  Vasanta Kumar Palisetti ,  Thomas Elmer ,  Kiran K Seshadri ,  FNU Arun Kumar

IPC: G06F15/80 ,  G06F7/53 ,  G06F7/544 ,  G06F7/505 ,  G06F9/30 ,  G06F9/38

Abstract: Systems and methods are provided to enable parallelized multiply-accumulate operations in a systolic array. Each row of the systolic array can include multiple busses enabling independent transmission of inputs along the respective bus. Each processing element of a given row-oriented bus can receive an input from a prior element of the given row-oriented bus, and perform arithmetic operations on the input. Each processing element can generate an output partial sum based on the arithmetic operations, provide the input to a next processing element of the given row-oriented bus, without the input being processed by a processing element of the row located between the two processing elements that uses a different row-oriented bus. Use of row-oriented busses can enable parallelization to increase speed or enable increased latency at individual processing elements.