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    Multiple accumulate busses in a systolic array
    1.
    发明授权
    Multiple accumulate busses in a systolic array 有权

    公开(公告)号：US11762803B2

    公开(公告)日：2023-09-19

    申请号：US17659642

    申请日：2022-04-18

    Applicant: Amazon Technologies, Inc.

    Inventor： Thomas A Volpe ,  Sundeep Amirineni ,  Thomas Elmer

    IPC: G06F15/80 ,  G06F7/53 ,  G06F7/544 ,  G06F7/505 ,  G06F9/30 ,  G06F9/38

    CPC classification number: G06F15/8046 ,  G06F7/505 ,  G06F7/53 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/3893

    Abstract: Systems and methods are provided to enable parallelized multiply-accumulate operations in a systolic array. Each column of the systolic array can include multiple busses enabling independent transmission of input partial sums along the respective bus. Each processing element of a given columnar bus can receive an input partial sum from a prior element of the given columnar bus, and perform arithmetic operations on the input partial sum. Each processing element can generate an output partial sum based on the arithmetic operations, provide the output partial sum to a next processing element of the given columnar bus, without the output partial sum being processed by a processing element of the column located between the two processing elements that uses a different columnar bus. Use of columnar busses can enable parallelization to increase speed or enable increased latency at individual processing elements.

    Multiple busses within a systolic array processing element
    3.
    发明授权
    Multiple busses within a systolic array processing element 有权

    公开(公告)号：US11422773B1

    公开(公告)日：2022-08-23

    申请号：US16915937

    申请日：2020-06-29

    Applicant: Amazon Technologies, Inc.

    Inventor： Thomas A Volpe ,  Thomas Elmer ,  Kiran K Seshadri

    IPC: G06F7/50 ,  G06F7/523 ,  G06F15/80 ,  G06F7/544 ,  G06F9/30

    Abstract: Systems and methods are provided to enable parallelized multiply-accumulate operations in a systolic array. Each row of the systolic array can include multiple busses enabling independent transmission of inputs along the respective bus. Each processing element can include a plurality of interconnects to receive a plurality of inputs corresponding to the multiple busses. Each processing element of a given row-oriented bus can receive an input from a prior element of the given row-oriented bus at an active bus position and perform arithmetic operations on the input. Each processing element can further receive a plurality of inputs at passive bus positions and provide the plurality of inputs to subsequent processing elements without the plurality of inputs being processed by the processing element. Use of row-oriented busses can enable parallelization to increase speed or enable increased latency at individual processing elements.

    Systolic array with efficient input reduction and extended array performance
    6.
    发明授权
    Systolic array with efficient input reduction and extended array performance 有权

    公开(公告)号：US11880682B2

    公开(公告)日：2024-01-23

    申请号：US17363894

    申请日：2021-06-30

    Applicant: Amazon Technologies, Inc.

    Inventor： Paul Gilbert Meyer ,  Thomas A Volpe ,  Ron Diamant ,  Joshua Wayne Bowman ,  Nishith Desai ,  Thomas Elmer

    IPC: G06F9/30 ,  G06F15/80

    CPC classification number: G06F9/3001 ,  G06F15/8046

    Abstract: Systems and methods are provided to perform multiply-accumulate operations of reduced precision numbers in a systolic array. Each row of the systolic array can receive reduced inputs from a respective reducer. The reduced input can include a reduced input data element and/or a reduced weight. The systolic array may lack support for inputs with a first bit-length and the reducers may reduce the bit-length of a given input from the first bit-length to a second shorter bit-length and provide the reduced input to the array. In order to reduce the bit-length, the reducer may reduce the number of trailing bits of the input. Further, the systolic array can receive a reduced and rounded input. The systolic array can propagate the reduced input through the processing elements in the systolic array. Each processing element may include a multiplier and/or an adder to perform arithmetical operations based on the reduced input.

    Multiple busses interleaved in a systolic array
    7.
    发明授权
    Multiple busses interleaved in a systolic array 有权

    公开(公告)号：US11308026B1

    公开(公告)日：2022-04-19

    申请号：US16915777

    申请日：2020-06-29

    Applicant: Amazon Technologies, Inc.

    Inventor： Thomas A Volpe ,  Vasanta Kumar Palisetti ,  Thomas Elmer ,  Kiran K Seshadri ,  FNU Arun Kumar

    IPC: G06F15/80 ,  G06F7/53 ,  G06F7/544 ,  G06F7/505 ,  G06F9/30 ,  G06F9/38

    Abstract: Systems and methods are provided to enable parallelized multiply-accumulate operations in a systolic array. Each row of the systolic array can include multiple busses enabling independent transmission of inputs along the respective bus. Each processing element of a given row-oriented bus can receive an input from a prior element of the given row-oriented bus, and perform arithmetic operations on the input. Each processing element can generate an output partial sum based on the arithmetic operations, provide the input to a next processing element of the given row-oriented bus, without the input being processed by a processing element of the row located between the two processing elements that uses a different row-oriented bus. Use of row-oriented busses can enable parallelization to increase speed or enable increased latency at individual processing elements.

    SYSTOLIC ARRAY WITH EFFICIENT INPUT REDUCTION AND EXTENDED ARRAY PERFORMANCE
    8.
    发明申请
    SYSTOLIC ARRAY WITH EFFICIENT INPUT REDUCTION AND EXTENDED ARRAY PERFORMANCE 有权

    公开(公告)号：US20230004384A1

    公开(公告)日：2023-01-05

    申请号：US17363894

    申请日：2021-06-30

    Applicant: Amazon Technologies, Inc.

    Inventor： Paul Gilbert Meyer ,  Thomas A Volpe ,  Ron Diamant ,  Joshua Wayne Bowman ,  Nishith Desai ,  Thomas Elmer

    IPC: G06F9/30 ,  G06F15/80

    Abstract: Systems and methods are provided to perform multiply-accumulate operations of reduced precision numbers in a systolic array. Each row of the systolic array can receive reduced inputs from a respective reducer. The reduced input can include a reduced input data element and/or a reduced weight. The systolic array may lack support for inputs with a first bit-length and the reducers may reduce the bit-length of a given input from the first bit-length to a second shorter bit-length and provide the reduced input to the array. In order to reduce the bit-length, the reducer may reduce the number of trailing bits of the input. Further, the systolic array can receive a reduced and rounded input. The systolic array can propagate the reduced input through the processing elements in the systolic array. Each processing element may include a multiplier and/or an adder to perform arithmetical operations based on the reduced input.

    MULTIPLE ACCUMULATE BUSSES IN A SYSTOLIC ARRAY
    9.
    发明申请
    MULTIPLE ACCUMULATE BUSSES IN A SYSTOLIC ARRAY 有权

    公开(公告)号：US20220350775A1

    公开(公告)日：2022-11-03

    申请号：US17659642

    申请日：2022-04-18

    Applicant: Amazon Technologies, Inc.

    Inventor： Thomas A Volpe ,  Sundeep Amirineni ,  Thomas Elmer

    IPC: G06F15/80 ,  G06F7/53 ,  G06F7/544 ,  G06F7/505

    Abstract: Systems and methods are provided to enable parallelized multiply-accumulate operations in a systolic array. Each column of the systolic array can include multiple busses enabling independent transmission of input partial sums along the respective bus. Each processing element of a given columnar bus can receive an input partial sum from a prior element of the given columnar bus, and perform arithmetic operations on the input partial sum. Each processing element can generate an output partial sum based on the arithmetic operations, provide the output partial sum to a next processing element of the given columnar bus, without the output partial sum being processed by a processing element of the column located between the two processing elements that uses a different columnar bus. Use of columnar busses can enable parallelization to increase speed or enable increased latency at individual processing elements.

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