公开(公告)号：US11748253B1

公开(公告)日：2023-09-05

申请号：US17449580

申请日：2021-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Suresh Hariharan ,  Kun Xu

IPC: G06F12/02 ,  G06F12/1081 ,  G06F13/16 ,  G06F15/173 ,  G06N3/04

CPC classification number: G06F12/0238 ,  G06F12/1081 ,  G06F13/1668 ,  G06F15/17375 ,  G06N3/04

Abstract: To generate sequential addresses when multiple integrated circuit (IC) devices are accessing a memory region, an address token is sent along the IC devices communicatively coupled in a ring topology. The address token includes a data increment value for the memory region. When a device receives the address token, a memory write address is determined based on the data increment value and a base address corresponding to the memory region for the current write cycle. The IC device can perform a write operation using the memory write address if the device has data to write. The data increment value of the address token is then updated based on the number of data units being written in the current write cycle to the memory region by the IC device, and the updated address token is transmitted to the next IC device of the ring topology.

公开(公告)号：US11789859B1

公开(公告)日：2023-10-17

申请号：US17449579

申请日：2021-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Kun Xu ,  Suresh Hariharan

IPC: G06F12/02 ,  G06F12/0855 ,  G06N3/063 ,  G06F15/173 ,  G06F12/1081

CPC classification number: G06F12/0238 ,  G06F12/0857 ,  G06F12/1081 ,  G06F15/17375 ,  G06N3/063

Abstract: To generate sequential addresses when multiple integrated circuit (IC) devices are accessing the same memory, an address token is sent along the IC devices communicatively coupled in a ring topology. The address token is first transferred along the ring topology during a memory reservation phase in which each IC device can set a corresponding memory request bit to indicate that the IC device has data to write to the memory. The modified address token is then transferred along the ring topology again during a memory access phase. During the memory access phase, each IC device that has data to write can perform a memory write operation using a sequential address determined from the contents of the address token.