Input/output voltage testing with boundary scan bypass

    公开(公告)号:US11567130B1

    公开(公告)日:2023-01-31

    申请号:US17247217

    申请日:2020-12-03

    Abstract: An integrated circuit device may include core circuitry, and a set of external interface buffer circuits coupled to the core circuitry. To improve test time and accuracy, as well as to simplify test procedures during voltage testing of the set of external interface buffer circuits, the integrated circuit device may include a test circuit and a combinational logic circuit coupled to the set of external interface buffer circuits. The combinational logic circuit is configured to combine a logic level of each of the external interface buffer circuits into a test signal, and the test circuit is configured to execute a voltage test on the set of external interface buffer circuits based on a logic level of the test signal.

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